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I2c buses
This document provides an overview of the Inter-Integrated Circuit (I2C) bus. It describes the key features and evolution of I2C buses, including their simplicity, flexibility, addressing schemes, and ability to support multiple masters. The document also details the I2C bus architecture, protocol for data communication including start/stop conditions and bit transfers, and how the Microchip Master Synchronous Serial Port module is used to implement I2C functionality.
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I2c buses
- 1. BY: NAVEEN KUMAR DUBEY BUSES (InterIntegrated Circuit Bus) CI2 2/13/2015 1 @naveen_elex
- 2. OUTLINES:- I2C-Bus:Introduction KeyFeatures of I2C Buses Development of I2C I2C Bus Architecture The I2C Bus Protocol MSSP Module in I2C buses Conclusion References 2/13/2015 2
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- 4. I2C-Bus:INTRODUCTION The I2Cbus was designed by Philips in the early '80s to allow easy communication between components which reside on the same circuit board. Philips Semiconductors migrated to NXP in 2006. The name I²C translates into "Inter IC". Sometimes the bus is called IIC . 2/13/2015 4
- 5. INRODUCTION (Contd…) Theoriginal communication speed was defined with a maximum rate of 100 kbit per second. There are some more speed options are available Fast mode - Speed 400 Kilo bit per second. High speed Mode – Speed 3.4 Mega Bit per second ( available since 1998) Recently a “Fast plus mode (introduced in 2007 by NXP)” which speed lies in between above two modes. 2/13/2015 5
- 6. Key Featuresof I2C Buses Simplicity and flexibility are key characteristics that make this bus attractive to many applications. Most significant features include: Only two bus lines are required (SDA & SCL ) No strict baud rate requirements like for instance with RS232 Simple master/slave relationships exist between all components . Each device connected to the bus is software-addressable by a unique address . I2C is a true multi-master bus providing arbitration and collision detection . 2/13/2015 6
- 7. Key Features (contd….) As per recent development there are few more features The Ultra Fast-mode is a uni-directional mode with data transfers of up to 5 Mbit/s. Some intelligent control, usually with a single-chip microcontroller On-chip filtering rejects spikes on the bus data line to preserve data integrity. 2/13/2015 7
- 8. Generation wisedevelopment of I2C Original 1982 - first release v1.0 1992 - Version 1.0 (of the I2C-bus specification) v2.0 1998 - This updated version of the I2C-bus specification meets requirements like higher bus speeds and lower supply voltages. v2.1 2000 - Version 2.1 (of the I2C-bus specification ) 2/13/2015 8
- 9. Contd…. v.3 -(19th June 2007 introduced by NXP ) Fast mode plus introduced in this version. v.4 - (13th Feb 2012 ) & V.5 - (19th October 2012) These are user manual release . 2/13/2015 9
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- 11. I2C Architecture(contd..) Master device is the one which initiates/ terminates data transfer and generates clock signals. Slave is a device addressed by Master. Both the master as well as slave can receive and transmit data . In I2C communication, a master controller always generates clock (SCL) however data can be generated by both. 2/13/2015 11
- 12. I2C Protocol (DataCommunication Process) 2/13/2015 12
- 13. Protocol (contd..) AddressFormats of I2C In I2C buses 7 bit as well as 10 bit addressing is possible. Hence 128 or 1024 slave devices can be addressed . In Case of 7 bit addressing one address byte is transmitted. In case of 10 bit addressing two address bytes are transmitted over SDA line. 2/13/2015 13
- 14. Protocol (contd..) 7 bitaddressing 10 bit addressing S 1 MSB 2 3 4 5 6 7 LSB R/W R 2/13/2015 14
- 15. Protocol (contd..) Addressing &Device detection Each device is addressed individually by software. New function or address can be easily “imposed” on to an existing bus. master Slave-1 Slave-2 Slave-3 2/13/2015 15
- 16. Protocol (contd..) Communication Communicationmust start with : START condition Start bit always followed bye Slave address. Slave address always followed by Read/Write bit The device must always send ACKNOWLEDGE bit (either master or slave) Communication must terminate with : STOP condition 2/13/2015 16
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- 18. Protocol (contd..) Start &Stop Condition Start Condition – A high to low transition on SDA when SCL is high. Stop Condition – A low to high transition on SDA when SCL is high. 2/13/2015 18
- 19. Protocol (contd..) Bit Transfer DuringData transfer SDA must be stable when SCL is high. 2/13/2015 19
- 20. Protocol (contd..) Data Transfer& Clock Stretching Each byte has to followed by Acknowledge Bit. Number of Byte transferred per transfer is unrestricted . If slave can’t receive or transmit another complete byte of data, it can hold the clock line SCL LOW (clock stretching) to force the master in to wait state. 2/13/2015 20
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- 22. Protocol (contd..) Acknowledge /Not Acknowledge 2/13/2015 22
- 23. Scenario with NACK(not acknowledge ) Condition A receiver with the address is not present on I2C bus The receiver is performing real time task and can not process information received from I2C bus. A receiver is master and want to take control on SDA to generate STOP command. The slave transmitter must release SDA after reception of NACK ,so that master can generate STOP. 2/13/2015 23
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- 25. MSSP Modulein I2C buses The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. Developed by Microchip . MSSP Modes The MSSP module can operate in two modes: Serial Peripheral Interface (SPI) - Full Master mode - Slave mode (with general address call) Inter-Integrated Circuit (I2C) - Master mode - Multi-Master mode - Slave mode 2/13/2015 25
- 26. Module Setup Toconfigure the MSSP module for Master I2C mode, there are key SFR registers which must be initialized. Respective code examples are shown for each. 1. SSP Control Register1 (SSPCON1) • I2C Mode Configuration 2. SSP Address Register (SSPADD) • I2C Bit Rate 3. SSP Status Register (SSPSTAT) • Slew Rate Control • Input Pin Threshold Levels ( I2C) 4. Pin Direction Control (TRISC) • SCL/SDA Direction 2/13/2015 26
- 27. 2/13/2015 27 I2C MODECONFIGURATION BIT RATE CALCULATION
- 28. 2/13/2015 28 I2C BIT RATESETUP SLEW RATE CONTROL
- 29. 2/13/2015 29 SCL/SDA PIN DIRECTIONSETUP ACKNOWLEDGE EVENT
- 30. 2/13/2015 30 NOT ACKNOWLEDGE EVENT STARTEVENT COMPLETION CHECK
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- 33. Conclusion 2/13/2015 33 The I2C-bushas become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher bus speeds and lower supply voltages. The updated version of the I2C-bus specification meets those requirements.
- 34. References http://www.i2c-bus.org/ http://www.nxp.com/documents/user_manual/UM 10204.pdf The I2C BusSpecification, version 2.1, January 2000 http://www.semiconductors.philips.com/buses/i2c www.phxmicro.com/Animation/I2C_Tutorial.htm http://ww1.microchip.com/downloads/en/appnotes 2/13/2015 34
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Editor's Notes
- #15 The first byte (immediately after the START condition) contains the I2C slave address. The I2C address is 7-bits long. It is transmitted in the seven most significant bits (MSB). The last (eighth bit) of the I2C address byte is a data direction bit (a read/write bit).
- #16 112 different address with the 7 bit formats (other reserved)