Asic design flow

Asic design flow

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  K.YOGESHWARAN ASSISTANT PROFESSOR/ECE KIT-KALAIGNARKARUNANIDHI INSTITUTEOF TECHNOLOGY,CIOMBATORE emperoryogi.yogesh@gmail.com 9789631474 ASIC DESGIN FLOW
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  Design Flow
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  LOGICAL DESIGN(FRONTEND) Consistsof following steps 1.Design Entry 2.Logic Synthesis 3.System Partitioning 4.Pre Layout Simulation PHYSICAL DESIGN(BACKEND) Consists of following steps 1.Floorplanning 2.Placement 3.Routing 4.Circuit Extraction 5.Post Layout Simulation
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  1. Design entry- Using a hardware description language ( HDL ) or schematic entry 2. Logic synthesis - Produces a netlist - logic cells and their connections 3. System partitioning - Divide a large system into ASIC-sized pieces 4. Prelayout simulation - Check to see if the design functions correctly 5. Floorplanning - Arrange the blocks of the netlist on the chip 6. Placement - Decide the locations of cells in a block 7. Routing - Make the connections between cells and blocks 8. Extraction - Determine the resistance and capacitance of the interconnect 9. Postlayout simulation - Check to see the design still works with the added loads of the interconnect
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  1.Design Entry  Thedesigner starts the design with a text description or system specific language like HDL, C language etc. 2.Logic Synthesis Logic synthesis is the process of converting a high- level description of design into an optimized gate-level representation. It generally helps to produce the netlist consisting the description and interconnection of logic cells.
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  3.System Partitioning  Goal:Partition of a System into number of ASIC’s  Objective: Minimize the number of external connection between each ASIC. Keep each ASIC smaller than max size.
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  Partitioning of alarge design into a small ASIC design takes place. This is done mainly to separate different functional blocks and also to make placement and routing easier.
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  4.Pre Layout Simulation PrelayoutSimulation allows checking whether the design functions correct or not. Gate level functionality and timing(Delay) details can be verified. It is also called as Functional Verification.
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  5.Floorplanning Goal: Calculate thesize of blocks and assign them locations. Objective: Keep highly connected blocks physically close to each other. It is the first step in the physical design flow. Arrange the blocks of the netlist on the chip. It is the Tentative placement of its major functional blocks.
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  Slicing Floorplan: One thatcan be obtained by repetitively subdividing (slicing) rectangles horizontally or vertically. Non-Slicing Floorplan: One that may not be obtained by repetitively subdividing alone.
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  6.Placement Goal: Assign theinterconnect areas and the locations of all the logic cells with in the flexible block. Objective: Minimize the ASIC area and the interconnects. Allows the placement of cells present in the block. Assigns exact locations for various circuit components within the chip’s core area. Placement is much more suited to automation than Floorplanning.
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  7.Routing  Make theconnections between cells and blocks.  It is the process of creating physical connections based on logical connectivity. signal pins are connected by routing metal interconnects. Global Routing:  Goal: Determine the location of all the interconnects. Objective: Minimize the total interconnect area.  Wire segments are tentatively assigned (embedded) within the chip layout .
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  Detailed Routing:  Goal:Completely route all the interconnects on the chip.  Objective: Minimize the total interconnect length used.  Find actual geometric layout of each net within assigned routing regions.
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  8.Circuit Extraction  Determinethe resistance and capacitance of the interconnect.  Basically it’s link between two domains. 1.Physical Domain 2.Electrical Domain  Physical domain -it’s uses the physical information like shapes of the design.  Electrical domain-provide the electrical information's (connectivity of C,R,L)
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  9.Postlayout simulation Post-layout simulationyou can extract the parasitic interconnect. To verify that your functional stimulus still works with accurate timing.
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