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![Arrays:
An array is a collection of variables, all of the same type, and accessed using the
same name plus one or more indices.
There are different types of arrays:
Examples:
int array1 [6]; //fixed size single dimension array
int array2 [5:0]; //fixed size single dimension array
int array3 [3:0][2:0]; //fixed size multi dimension array
bit [7:0] array4[2:0]; //unpacked array declaration
bit [2:0][7:0] array5; //packed array declaration
bit [2:0][7:0] array6 [3]; //mixed packed and unpacked array](https://image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-15-2048.jpg)
![Fixed array:
In fixed size array, array size will be constant throughout the simulation,
Once the array is declared no need to create it.
By default, the array will be initialized with value ‘0’.
Single Dimension array:
int array1 [6]; //Compact declaration
int array2 [5:0]; // Verbose declaration
Two Dimension array:
int arr[2][3];
Three Dimension array:
int arr[2][2][2];
Array assignment:
array = '{ '{0,1,2,3},'{4,5,6,7},'{8,9,10,11}};](https://image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-16-2048.jpg)
![Dynamic array:
A dynamic array is one dimension of an unpacked array whose size can be set or
changed at run-time.
Dynamic array is Declared using an empty word subscript [ ].
The space for a dynamic array doesn’t exist until the array is explicitly created at
run-time, space is allocated when new[number] is called.
The number indicates the number of space/elements to be allocated.
Dynamic arrays are useful for contiguous collections of variables whose number
changes dynamically.
Syntax:
Data_type array_name[];
Methods:
new[ ] –> allocates the storage.
size( ) –> returns the current size of a dynamic array.
delete( ) –> empties the array, resulting in a zero-sized array.](https://image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-19-2048.jpg)
![Associative Array:
Associative array Stores entries in a sparse matrix.
Associative arrays allocate the storage only when it is used, unless like in the
dynamic array we need to allocate memory before using it.
In associative array index expression is not restricted to integral expressions,
but can be of any type.
When the size of the collection is unknown or the data space is sparse, an
associative array is a better option.
Syntax:
data_type array_name [ index_type ];](https://image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-21-2048.jpg)
![Associative array:
Examples:
int a_array1[*] ; // associative array of integer (unspecified index)
bit [31:0] a_array2[string]; // associative array of 32-bit, indexed by string
ev_array [myClass]; //associative array of event, indexed by class](https://image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-22-2048.jpg)
![Queue:
A queue is a variable-size, ordered collection of homogeneous elements.
Like a dynamic array, queues can grow and shrink.
Queue supports adding and removing elements anywhere.
Queues are declared using the same syntax as unpacked arrays, but specifying
$ as the array size. In queue 0 represents the first, and $ representing the last
entries.
Syntax:
Data_type queue_name[$];
Example:
bit queue_1[$]; // queue of bits (unbound queue)
int queue_2[$]; // queue of int
byte queue_3[$:255]; // queue of byte (bounded queue with 256 entries)
string queue_4[$]; // queue of strings](https://image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-24-2048.jpg)
![Arrays:
An array is a collection of variables, all of the same type, and accessed using the
same name plus one or more indices.
There are different types of arrays:
Examples:
int array1 [6]; //fixed size single dimension array
int array2 [5:0]; //fixed size single dimension array
int array3 [3:0][2:0]; //fixed size multi dimension array
bit [7:0] array4[2:0]; //unpacked array declaration
bit [2:0][7:0] array5; //packed array declaration
bit [2:0][7:0] array6 [3]; //mixed packed and unpacked array](https://crownmelresort.com/image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-15-2048.jpg)
![Fixed array:
In fixed size array, array size will be constant throughout the simulation,
Once the array is declared no need to create it.
By default, the array will be initialized with value ‘0’.
Single Dimension array:
int array1 [6]; //Compact declaration
int array2 [5:0]; // Verbose declaration
Two Dimension array:
int arr[2][3];
Three Dimension array:
int arr[2][2][2];
Array assignment:
array = '{ '{0,1,2,3},'{4,5,6,7},'{8,9,10,11}};](https://crownmelresort.com/image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-16-2048.jpg)
![Dynamic array:
A dynamic array is one dimension of an unpacked array whose size can be set or
changed at run-time.
Dynamic array is Declared using an empty word subscript [ ].
The space for a dynamic array doesn’t exist until the array is explicitly created at
run-time, space is allocated when new[number] is called.
The number indicates the number of space/elements to be allocated.
Dynamic arrays are useful for contiguous collections of variables whose number
changes dynamically.
Syntax:
Data_type array_name[];
Methods:
new[ ] –> allocates the storage.
size( ) –> returns the current size of a dynamic array.
delete( ) –> empties the array, resulting in a zero-sized array.](https://crownmelresort.com/image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-19-2048.jpg)
![Associative Array:
Associative array Stores entries in a sparse matrix.
Associative arrays allocate the storage only when it is used, unless like in the
dynamic array we need to allocate memory before using it.
In associative array index expression is not restricted to integral expressions,
but can be of any type.
When the size of the collection is unknown or the data space is sparse, an
associative array is a better option.
Syntax:
data_type array_name [ index_type ];](https://crownmelresort.com/image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-21-2048.jpg)
![Associative array:
Examples:
int a_array1[*] ; // associative array of integer (unspecified index)
bit [31:0] a_array2[string]; // associative array of 32-bit, indexed by string
ev_array [myClass]; //associative array of event, indexed by class](https://crownmelresort.com/image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-22-2048.jpg)
![Queue:
A queue is a variable-size, ordered collection of homogeneous elements.
Like a dynamic array, queues can grow and shrink.
Queue supports adding and removing elements anywhere.
Queues are declared using the same syntax as unpacked arrays, but specifying
$ as the array size. In queue 0 represents the first, and $ representing the last
entries.
Syntax:
Data_type queue_name[$];
Example:
bit queue_1[$]; // queue of bits (unbound queue)
int queue_2[$]; // queue of int
byte queue_3[$:255]; // queue of byte (bounded queue with 256 entries)
string queue_4[$]; // queue of strings](https://crownmelresort.com/image.slidesharecdn.com/systemverilogbychinnifinal-201114060759/75/Introduction-to-System-verilog-24-2048.jpg)
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Introduction to System verilog
- 1.
- 2. Introduction: What issystem Verilog? Why we go for System Verilog? What is verification? How to verify Design? Why system Verilog for verification? Evolution of System Verilog System Verilog Features Data Types
- 3. What is SystemVerilog? System Verilog is a hardware description and hardware verification language. System Verilog is used to model, design, simulate, test and implement electronic systems. System Verilog is based on Verilog and some extensions. What is Hardware Description Language? Hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits. What is Hardware Verification Language? Hardware verification language(HVL) is a programming language used to verify the designs of electronic circuits written in a HDL.
- 4. Why we gofor System Verilog? Verilog was the primary language to verify functionality of designs that were small, not very complex and had less features. As design complexity increase, so does the requirement of better tools to design and verify it. System Verilog is far superior to Verilog because of its ability to perform constraint random stimulus, use oops features in testbench construction, functional coverage, assertions among many others.
- 5. What is verification? Verification is the process of ensuring that a given hardware design works as expected. Make sure design is bug free by verifying it in all aspects. All possible scenarios. Example:
- 6. How to verifyDUT?
- 7. Why system Verilogfor verification? Verilog was initially used for writing testbench. But, writing complex testbench is much more of programming task than describing hardware. No need to synthesize testbench. Now UVM is replacing SV based verification in industry. Still, UVM = Structured SV. knowing SV based verification helps understanding UVM based verification, else UVM feels like set of magic macros.
- 8. Evaluation of SV: SystemVerilog language components are: • Concepts of Verilog HDL. • Testbench constructs based on Vera. • Open Vera assertions. • Synopsys’ VCS DirectC simulation interface to C and C++. • A coverage application programming interface that provides links to coverage metrics.
- 9.
- 10. Data Types: What isdata type? • In programming, data type is a classification that specifies which type of value a variable has. • For example, A string, is a data type that is used to classify text. • An integer is a data type used to classify whole numbers.
- 11. Data Types: SystemVerilogadded lot of new data types and improved the existing data types to improve run time memory utilization of simulators. In System Verilog data types can be classified into 2-state types and 4-state types. 2-state types can take only 0, 1, where as 4-state types can take 0,1,X,Z. 2-state types consume less (50%) memory and simulate faster when compared to 4-state types. SV introduces a new 4-state data type called logic that can be driven in both procedural blocks and continuous assign statements. But, a signal with more than one driver needs to be declared a net-type such as wire so that System Verilog can resolve the final value.
- 12.
- 13.
- 14. Void Data Type: void is used in functions to return no value. Void data type represents non-existent data. This type can be specified as the return type of function, including no return value. Syntax: function void display (); $display ("Am not going to return any value"); endfunction
- 15. Arrays: An arrayis a collection of variables, all of the same type, and accessed using the same name plus one or more indices. There are different types of arrays: Examples: int array1 [6]; //fixed size single dimension array int array2 [5:0]; //fixed size single dimension array int array3 [3:0][2:0]; //fixed size multi dimension array bit [7:0] array4[2:0]; //unpacked array declaration bit [2:0][7:0] array5; //packed array declaration bit [2:0][7:0] array6 [3]; //mixed packed and unpacked array
- 16. Fixed array: Infixed size array, array size will be constant throughout the simulation, Once the array is declared no need to create it. By default, the array will be initialized with value ‘0’. Single Dimension array: int array1 [6]; //Compact declaration int array2 [5:0]; // Verbose declaration Two Dimension array: int arr[2][3]; Three Dimension array: int arr[2][2][2]; Array assignment: array = '{ '{0,1,2,3},'{4,5,6,7},'{8,9,10,11}};
- 17. Packed Array: Theterm packed array is used to refer to the dimensions declared before the data identifier name. Packed arrays can be of single bit data types (reg, logic, bit), enumerated types. A packed array is guaranteed to be represented as a contiguous set of bits. Example:
- 18. Unpacked array: Theterm unpacked array is used to refer to the dimensions declared after the data identifier name. Unpacked arrays can be of any data type. An unpacked array may or may not be so represented as a contiguous set of bits. Example:
- 19. Dynamic array: Adynamic array is one dimension of an unpacked array whose size can be set or changed at run-time. Dynamic array is Declared using an empty word subscript [ ]. The space for a dynamic array doesn’t exist until the array is explicitly created at run-time, space is allocated when new[number] is called. The number indicates the number of space/elements to be allocated. Dynamic arrays are useful for contiguous collections of variables whose number changes dynamically. Syntax: Data_type array_name[]; Methods: new[ ] –> allocates the storage. size( ) –> returns the current size of a dynamic array. delete( ) –> empties the array, resulting in a zero-sized array.
- 20.
- 21. Associative Array: Associativearray Stores entries in a sparse matrix. Associative arrays allocate the storage only when it is used, unless like in the dynamic array we need to allocate memory before using it. In associative array index expression is not restricted to integral expressions, but can be of any type. When the size of the collection is unknown or the data space is sparse, an associative array is a better option. Syntax: data_type array_name [ index_type ];
- 22. Associative array: Examples: int a_array1[*]; // associative array of integer (unspecified index) bit [31:0] a_array2[string]; // associative array of 32-bit, indexed by string ev_array [myClass]; //associative array of event, indexed by class
- 23.
- 24. Queue: A queueis a variable-size, ordered collection of homogeneous elements. Like a dynamic array, queues can grow and shrink. Queue supports adding and removing elements anywhere. Queues are declared using the same syntax as unpacked arrays, but specifying $ as the array size. In queue 0 represents the first, and $ representing the last entries. Syntax: Data_type queue_name[$]; Example: bit queue_1[$]; // queue of bits (unbound queue) int queue_2[$]; // queue of int byte queue_3[$:255]; // queue of byte (bounded queue with 256 entries) string queue_4[$]; // queue of strings
- 25. Queue: A queuecan be bounded or unbounded. bounded queue – queue with the number of entries limited or queue size specified.
- 26. Queue: unbounded queue –queue with unlimited entries or queue size not specified.
- 27.
- 28.
- 29. Events: Events arestatic objects useful for synchronization between the process. Events operations are of two staged processes in which one process will trigger the event, and the other processes will wait for an event to be triggered. Events are triggered using -> operator or ->> operator wait for an event to be triggered using @ operator or wait() construct System Verilog events act as handles to synchronization queues. thus, they can be passed as arguments to tasks, and they can be assigned to one another or compared. Syntax: ->event_name; @(event_name.triggered);
- 30. Structure & Union: A structure is a user-defined data type. that allows to combining data items of different kinds. Structures are used to represent a record. Like Structures, union is a user defined data type. In union, all members share the same memory location. Example:
- 31. Classes: A classis a user-defined data type. Classes consist of data (called properties) and tasks and functions to access the data (called methods). Classes are used in object-oriented programming. In SystemVerilog, classes support the following aspects of object-orientation – encapsulation, data hiding, inheritance and polymorphism. Example: class c; int x; task set (int i); x=1; endtask; endmodule;
- 32.