Sv data types and sv interface usage in uvm

Introduction
lVerilog has reg and wire data-types to describe hardware behavior.
lverification of hardware can become more complex and demanding, datatypes
in Verilog are not sufficient to develop efficient testbenches and testcases.
Hence SystemVerilog has extended Verilog by adding more C like data-types for
better encapsulation and compactness.

Basic SV data types
Data type 2/4 state bits Signed/unsigned
reg 4 >=1 unsigned
wire 4 >=1 unsigned
Integer 4 32 signed
real float
time 64 unsigned
realtime
logic 4 >=1 unsigned
bit 2 >=1 unsigned
byte 2 8 signed
int 2 16 signed
Short int 2 32 signed
Long int 2 64 signed

Values SystemVerilog variables can hold
0 Logic state 0 - element/net is at 0 volts
1 Logic state 1 - element/net is at some value > 0.7 volts
x Logic state X - element/net has either 0/1 - we just don't know
z Logic state Z - net has high impedence - maybe the wire is not
connected and is floating

String Data type
lString data type in SystemVerilog is a dynamic collection of
characters. Each character of the String variable is of type
“byte”.
lstring myName = "SV";

String Methods
lSystemVerilog also includes a number of special methods to work with strings. These methods
use the built-in method notation. These methods are:
l1. str.len() returns the length of the string, i.e., the number of characters in the string.
l2. str.putc(i, c) replaces the ith character in str with the given integral value.
l3. str.getc(i) returns the ASCII code of the ith character in str.
l4. str.toupper() returns a string with characters in str converted to uppercase.
l5. str.tolower() returns a string with characters in str converted to lowercase.
l6. str.compare(s) compares str and s, and return value. This comparison is case sensitive.
l7. str.icompare(s) compares str and s, and return value .This comparison is case insensitive.

SV User defined data types
Systemverilog allows the user to define datatypes.There are different ways to define user defined datatypes. They are
1.Enumarations.
2.Struct.
3.Union.
4.Typedef.
5.class
ENUM:
An enumerated type defines a set of named values. In the following example, light_1 is an enumerated variable
that can store one of the three possible values (0, 1, 2). By default, the first name in the enumerated list gets the value 0 and
the following names get incremental values like 1 and 2.
EX:
enum {RED, YELLOW, GREEN} light_1; // int type; RED=0,YELLOW=1,GREEN=2
enum bit[2:0] {RED, YELLOW=5, GREEN} light_2; // bit type;RED =0, YELLOW=5,GREEN =6
**Note that an enumeration name cannot start with a number !
enum {1WAY, 2TIMES, SIXPACK=6} e_formula; // Compilation error on 1WAY, 2TIMES

Enumerated type methods
lSystemVerilog includes a set of specialized methods to enable iterating over the values of enumerated types.
first() function enum first(); Returns the value of the first member of the
enumeration
last() function enum last(); Returns the value of the last member of the
enumeration
next() function enum next (int
unsigned N = 1);
Returns the Nth next enumeration value
starting from the current value of the given
variable
prev() function enum prev (int
unsigned N = 1);
Returns the Nth previous enumeration value
starting from the current value of the given
variable
num() function int num(); Returns the number of elements in the given
enumeration
name() function string name(); Returns the string representation of the
given enumeration value

STRUCTURES
lThe disadvantage of arrays is that all the elements stored in then are to be of the
same data type.
lIf we need to use a collection of different data types, it is not possible using an array.
When we require using a collection of different data items of different data types we
can use a structure.
lStructure is a method of packing data of different types. A structure is a convenient
method of handling a group of related data items of different data types.
lEX: struct {int a;byte b;bit [7:0] c;} my_data_struct;
lThe structured variables can be accessed using the variable name "my_data_struct".
lmy_data_struct.a = 123;
l$display(" a value is %d ",my_data_struct.a);

UNIOUNS
lUnions like structure contain members whose individual data types may differ
from one another.
lHowever the members that compose a union all share the same storage area.
lA union allows us to treat the same space in memory as a number of different
variables.
lThat is a Union offers a way for a section of memory to be treated as a variable
of one type on one occasion and as a different variable of a different type on
another occasion.
lunion {int a;byte b;bit [7:0] c;} my_data_union;
31 0
Bit[7:0]c / byte b / inta

TypeDef
lA typedef declaration lets you define your own identifiers that can be used in place of type
specifiers such as int, byte, real. Let us see an example of creating data type "nibble".
ltypedef bit[3:0] nibble; // Defining nibble data type.
lnibble a, b; // a and b are variables with nibble data types.
lAdvantages Of Using Typedef :
lShorter names are easier to type and reduce typing errors.
lImproves readability by shortening complex declarations.
lImproves understanding by clarifying the meaning of data.
lChanging a data type in one place is easier than changing all of its uses throughout the code.
lAllows defining new data types using structs, unions and Enumerations also.
lIncreases reusability.
lUseful is type casting.

Class Data type
lA class is a user-defined data type that includes data (class properties), functions and tasks that operate on
data.
lfunctions and tasks are called as methods, both are members of the class.
lclasses allow objects to be dynamically created, deleted, assigned and accessed via object handles.
lclass sv_class;
l int x;// //class properties
l task set(int i);// //method-1
l x = i;
l endtask
l function int get();// //method-2
l return x;
l endfunction
lendclass

Constant Data Types:
lIn SV, as per LRM definition Constants are the named data object
that never changes.
lSystemVerilog provide following 2 types of constants:
l Elaboration time constants
l Parameter constants (parameter, localparam)
l Run time constants
l const

Operaters & Expressions
lThe SystemVerilog operators are a combination of Verilog and C operators.
lIn both languages, the type and size of the operands is fixed, and hence the operator is of a
fixed type and size. The fixed type and size of operators is preserved in SystemVerilog.
lAn expression is a construct that combines operands with operators to produce a result that
is a function of the values of the operands and the semantic meaning of the operator.
lAn operand can be one of the following:
lConstant literal number, including real literals,String literal,Parameter, including local and
specify parameters,Net,Net bit-select or part-select,Variable bit-select or part-
select,Structure, either packed or unpacked,A call to a user-defined function, system-defined
function, or method that returns any of the above.

Assignment Operators
lSystemVerilog introduces the C assignment operators and special bitwise assignment operators: +=, -=, *=, /=,
%=, &=, |=, ^=, <<=, >>=, <<<=, and >>>=. The assignment operator is semantically equivalent to a blocking
assignment.

Increment and decrement operators
lSystemVerilog includes the C increment and decrement assignment operators ++i , --i , i++ , and i-- .
lThese increment and decrement assignment operators behave as blocking assignments.
lThe increment and decrement operators, when applied to real operands, increment or decrement the
operand by 1.0.
lEx:
li = 10;
lj = i++ + (i = i – 1);
lAfter execution, the value of j can be 18, 19, or 20 depending upon the relative ordering of the
increment and the assignment statements.

Arithmetic operators
lEX:
lprogram main;
linteger a,b;
linitial
lbegin
lb = 10;a = 22;
l$display(" -(nagetion) is %0d ",-(a) );
l$display(" a + b is %0d ",a+b);
l$display(" a - b is %0d ",a-b);
l$display(" a * b is %0d ",a*b);
l$display(" a / b is %0d ",a/b);
l$display(" a modulus b is %0d ",a%b);
lend
lendprogram

Relational operators
lAn expression using these relational operators shall yield the scalar value 0 if the specified relation is false or
the value 1 if it is true.
lIf either operand of a relational operator contains an unknown ( x ) or high-impedance ( z ) value, then the
result shall be a 1-bit unknown value ( x ).
lOperators are > ,>= ,<, <= .
lAll the relational operators shall have the same precedence. Relational operators shall have lower precedence
than arithmetic operators.

Equality operators
lAll four equality operators shall have the same precedence. These four operators compare
operands bit for bit. As with the relational operators, the result shall be 0 if comparison fails and 1 if
it succeeds.
lIf the operands are of unequal bit lengths, the smaller operand shall be zero-extended to thesize
of the larger operand.
la === b// a equal to b, including x and z
la !== b //a not equal to b, including x and z
la == b //a equal to b, result can be unknown
la != b //a not equal to b, result can be unknown

Wildcard equality operators
lThe wildcard equality operators shall have the same precedence as the equality operators.
lIf the operands to the wildcard equality/inequality are of unequal bit length, the operands are
extended in the same manner as for the logical equality/inequality operators.
l If the relation is true, the operator yields a 1. If the relation is false,it yields a 0. If the relation is
unknown, it yields X .
la ==? b //a equals b, X and Z values in b act as wildcards
la !=? b a does not equal b, X and Z values in b act as wildcards
lEX:
typedef enum logic [5:0] {S1=6'b100100, S2=6'b100111,S3=6'b100000} stage_e;
(stage_e ==? 6'b1??1??) would be true if stage had the value S1 or S2, and false for the
value S3. If stage had the uninitialized value 6'bx, it would evaluate to false.

Logical operators
lThe operators logical AND ( && ), logical OR ( || ), logical implication ( -> ), and logical
equivalence ( <-> ) are logical connectives.
lThe result of the evaluation of a logical operation shall be 1 (defined as true), 0 (defined as false),
or, if the result is ambiguous, the unknown value ( x ).
lThe precedence of && is greater than that of || , and both are lower than relational and equality
operators.
lThe logical implication expression1 –> expression2 is logically equivalent to
l(!expression1 || expression2) .
lThe logical equivalence expression1 <–> expression2 is logically equivalent to
l ((expression1 –> expression2) && (expression2 –> expression1)) .
lEx: If variable alpha holds the integer value 237 and beta holds the value zero, then the following
examples perform as described:
lregA = alpha && beta;// regA is set to 0
lregB = alpha || beta;// regB is set to 1

Bitwise operators
lThe bitwise operators shall perform bitwise manipulations on the operands.
lThe operator shall combine a bit in one operand with its corresponding bit in the other operand to
calculate 1 bit for the result.

Reduction operators
lThe unary reduction operators shall perform a bitwise operation on a single operand to produce a
single-bit result.
Operand & ~& | ~| ^ ~^ Comments
4'b0000 0 1 0 1 0 1 No bits set
4'b1111 1 0 1 0 0 1 All bits set
4'b0110 0 1 1 0 0 1 Even number of bits set
4'b1000 0 1 1 0 1 0 Odd number of bits set

Shift operators
lThere are two types of shift operators: the logical shift operators, << and >> , and the arithmetic
shift operators, <<< and >>> .
lThe left shift operators, << and <<< , shall shift their left operand to the left by the number of bit
positions given by the right operand.
lThe right shift operators, >> and >>> , shall shift their left operand to the right by the number of bit
positions given by the right operand.
lIn both cases, the vacated bit positions shall be filled with zeros.
lEx: In this example, the variable result is assigned the binary value 0100 , which is 0001 shifted
to the left two positions and zero-filled.
lmodule shift;
llogic [3:0] start, result;
linitial begin
lstart = 1;
lresult = (start << 2);
lend
lendmodule

Conditional operator
lThe conditional operator shall be right associative and shall be constructed using three operands
separated by two operators in the format given in syntax.
lcondition ? expression1 : expression2;
l Ex:(a) ? 4'b110x : 4'b1000;
lIf 'a' has a non-zero value then the result of this expression is 4'b110x. If 'a' is 0, then the result of
this expression is 4'b1000. If 'a' is x value then the result is 4'b1x0x (this is due to the fact that the
result must be calculated bit by bit on the basis of the Table)
lIf both expressions are real , then the resulting type is real . If one expression is real and the
other expression is shortreal or integral, the other expression is cast to real , and the resulting
type is real .
?: 0 1 x z
0 0 x x x
1 x 1 x x
x x x x x
z x x x x

Concatenation operators
lA concatenation is the result of the joining together of bits resulting from one or more
expressions. The concatenation shall be expressed using the brace characters { and } , with
commas separating the expressions within.
lUnsized constant numbers shall not be allowed in concatenations. This is because the size of
each operand in the concatenation is needed to calculate the complete size of the concatenation.
lThe following example concatenates four expressions:
l{a, b[3:0], w, 3'b101} equalent to {a, b[3], b[2], b[1], b[0], w, 1'b1, 1'b0, 1'b1}
lA replication operator (also called a multiple concatenation) is expressed by a concatenation
preceded by a non-negative, non- x , and non- z constant expression, called a replication
constant, enclosed together within brace characters.
lThis example replicates w four times.
l{4{w}} // yields the same value as {w, w, w, w}

OPERATOR PRECEDENCY
l() Highest precedence
l++ --
l& ~& | ~| ^ ~^ ~ >< -
l* / %
l+ -
l<< >>
l< <= > >=
l=?= !?= == != === !==
l& &~
l^ ^~
l| |~
l&&
l||
l?:
l= += -= *= /= %=
l<<= >>= &= |= ^= ~&= ~|= ~^= Lowest precedence

lIn Verilog, the communication between blocks is specified using module ports. SystemVerilog adds the
interface construct which encapsulates the communication between blocks.
lAn interface is a bundle of signals or nets through which a testbench communicates with a design. Fig
shows TB & DUT with and without interface.
lAn interface is a named bundle of wires, the interfaces aim is to encapsulate communication.

lInterface specifies the,
l directional information, i.e modports
l timing information, i.e clocking blocks
lAn interface can have parameters, constants, variables, functions, and tasks.
lAdvantages of the interface over the traditional connection,
l-allows the number of signals to be grouped together and represented as a single port, the single
port handle is passed instead of multiple signal/ports.
l-interface declaration is made once and the handle is passed across the modules/components.
l-addition and deletion of signals are easy.
l-Increases the reusability.
l- Reduces errors which can cause during module connections.

Modports
l To specify the direction of the signal w.r.t module which uses interface instead of port list,
modports are used.
lModport restrict interface access within a module based on the direction declared.
lEx:
linterface intf (input clk);
llogic read, enable,
llogic [7:0] addr,data;
lmodport dut (input read,enable,addr,output data);
lmodport tb (output read,enable,addr,input data);
lendinterface :intf

Clocking Block
lclocking block that identifies clock signals, and captures the timing and synchronization
requirements of the blocks being modeled.
lclocking cb @(posedge clk);
ldefault input #10ns output #2ns;
loutput read,enable,addr;
linput negedge data;
lEndclocking
lIn the above example, the first line declares a clocking block called cb that is to be clocked on the
positive edge of the signal clk.
l The second line specifies that by default all signals in the clocking block shall use a 10ns input
skew and a 2ns output skew by default.
lThe next line adds three output signals to the clocking block: read, enable and addr.
lThe fourth line adds the signal data to the clocking block as input. Fourth line also contains
negedge which overrides the skew ,so that data is sampled on the negedge of the clk.

Virtual Interface
lInterface is static in nature, whereas classes are dynamic in nature. because of this reason, it is
not allowed to declare the interface within classes, but it is allowed to refer to or point to the
interface.
lA virtual interface is a variable of an interface type that is used in classes to provide access to the
interface signals.
lVirtual interfaces provide a mechanism for separating abstract models and test programs from
the actual signals that make up the design.
lVirtual interface can be used to make the TestBench independent of the physical interface.
lA virtual interface must be initialized before it can be used, by default, it points to null. Attempting
to use an uninitialized virtual interface will result in a run-time error.
l Syntax
lvirtual interface_name instance_name;

Interface Passing to ENV
lUsing a virtual interface as a reference or handle to the interface instance, the testbench can
access the tasks, functions, ports, and internal variables of the SystemVerilog interface.
lAs the interface instance is connected to the DUT pins, the testbench can monitor and control the
DUT pins indirectly through the interface elements.
lThe recommended approach for passing this information to the testbench is to use either the
configuration database using the config_db API.

lStep #1: Placing a Virtual Interface into the Configuration
Database using the config_db
lmodule top_mac;// Top level module for a wishbone system with bus connection
l...
lwishbone_bus_syscon_if wb_bus_if(); // WISHBONE interface instance
l ...
l initial begin
l uvm_config_db #(virtual wishbone_bus_syscon_if)::set(null, "uvm_test_top",
"WB_BUS_IF", wb_bus_if); //set interfaces in config space
l run_test("test_mac_simple_duplex"); // create and start running test
l end
lendmodule

Step #2: Making the Virtual Interface Available in the Testbench
lTest class gets the virtual interface and places it into configuration object. This object can then be
accessed by all TB components.
lclass test_mac_simple_duplex extends uvm_test;
l.......
lwb_config wb_config_0; // config object for Virtual Interface
l function void build_phase(uvm_phase phase); //build_phase
l if (!uvm_config_db #(virtual wishbone_bus_syscon_if)::get(this, "", "WB_BUS_IF",
wb_config_0.v_wb_bus_if)) // virtual interface getting
l `uvm_fatal("TEST_MAC_SIMPLE_DUPLEX", "Can't read WB_BUS_IF");
l uvm_config_db#(wb_config)::set(this, "*", "wb_config", wb_config_0); // Place the Virtual
interface into Configuration object
l endfunction endclass
l

lclass wb_m_bus_driver extends uvm_driver #(wb_txn, wb_txn);
l...
l virtual wishbone_bus_syscon_if m_v_wb_bus_if; // Virtual Interface
l wb_config m_config;
l//Get the config DB for virtual interface
l function void build_phase(uvm_phase phase);
l super.build_phase(phase);
l if (!uvm_config_db #(wb_config)::get(this, "", "wb_config", m_config)) // get config object
l `uvm_fatal("Config Fatal", "Can't get the wb_config")
l ...
l endfunction : build_phase
Step #3: Assigning Virtual Interface Property to component that actually
accesses the DUT(Driver,moniter..)

l // Drive it to DUT using local Virtual Interface
l function void connect_phase(uvm_phase phase);
l super.connect_phase(phase);
l m_v_wb_bus_if = m_config.v_wb_bus_if; // set local virtual if property
l endfunction : connect_phase
l ...
lendclass

Sv data types and sv interface usage in uvm

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