Implementation of Full Adder Cell Using High Performance CMOS Technology

Implementation of Full Adder Cell Using High Performance CMOS Technology

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  IJSRD - InternationalJournal for Scientific Research & Development| Vol. 2, Issue 07, 2014 | ISSN (online): 2321-0613 All rights reserved by www.ijsrd.com 262 Implementation of Full Adder Cell Using High Performance CMOS Technology Shagun Sharma1 Ankita Aggarwal2 1 M.E Student 1,2 Department of Electronics and Communication Engineering 1,2 Galaxy Global Educational Trust Group of Institutions,(Affiliated To Kurukshetra University) Dinarpur, Ambala, Haryana Abstract— This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results. Keywords: Full adder, CMOS gates, Transistor logics, Sum, Carry I. INTRODUCTION One of the major dynamic power consumers in computing and consumer electronics products is the system’s clock signal, typically responsible for 30%–70% of the total dynamic power consumption. Several techniques to reduce the dynamic power are developed, of which clock gating is predominant. Ordinarily, when a logic unit is clocked, its underlying sequential elements receive the clock signal, regardless of whether or not they will toggle in the next cycle. With clock gating, the clock signals are ended with explicitly predefined enabling signals. Clock gating is employed at all levels: system architecture, block design, logic design, and gates. With the rapid increase in design complexity, computer aided design tools supporting system-level hardware description have become commonly used. Although substantially increasing design productivity, such tools require the employment of a long chain of automatic synthesis algorithms, from register transfer level (RTL) down to gate level and net list. A. CMOS Technology Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. CMOS is also sometimes referred to as complementary-symmetrymetal–oxide–semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor- transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips. The phrase "metal–oxide– semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor Material Aluminum was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and beyond. "CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.[3] As of 2010, CPUs with the best performance per watt each year have been CMOS static logic since 1976. CMOS circuits use a combination of p-type and n-type metal– oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. Although CMOS logic can be implemented with discrete devices (e.g., for instructional purposes in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions of transistors of both types on a rectangular piece of silicon of between 10 & 400mm2. These devices are commonly called "chips", although within the industry they are also referred to as "die" (singular) or "dice", or "dies" (plural).
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  Implementation of FullAdder Cell Using High Performance CMOS Technology (IJSRD/Vol. 2/Issue 07/2014/061) All rights reserved by www.ijsrd.com 263 B. CMOS Process Enhancements 1) Silicon on Insulator As the name suggests transistors are fabricated on an insulator (SiO2 or sapphire) Insulating substrate eliminates capacitance between the source/drain and body, higher speed devices and low leakage currents. 2) Transistors Multiple threshold voltages and oxide thicknesses Processes offer multiple threshold voltages Low threshold devices: faster, higher leakage. High threshold devices: opposite Thin oxides: provide high ON currents but cannot handle high voltages. High-k gate dielectrics Transistors need high gate capacitance to attract charge to the channel Thin gates and therefore high gate leakages Thicker gates that leak less can be made with high-k materials e.g. hafnium oxide (k=20), zirconium oxide (k=23), silicon nitride (k=6.5-7.5) Applied using ALD, MOCVD (metallo –organic CVD) or sputtering. C. Design and Architecture of Full Adder Fig. 1.1 The ultimate goal of a binary full-adder (BFA) is to implement the following truth table for each bit: C in A B Sum C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Table 1: Truth table for 1-bit adder slice Logically, carry = AB+BC+CA and Sum = C⊕B⊕A, where k is an integer 0 to n for an n-bit adder. Generally, adders of n-bits are created by chaining together n of these 1-bit adder slices. Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one- bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.A 1-bit full adder adds three one bit numbers, frequently written as A, B and C. A and B are the operands and C is a bit carried in from the next less important stage. Full adder is typically a part in a cascade of adders’ binary numbers [9]. The circuit generates a two-bit output sum typically represented by the signals Carry and Sum. Here a full adder is constructed with the help of two half adders by connecting A and B to the input of first half adder, connecting the sum from that to an input to the second adder, connecting C to the other input and OR the two carry outputs. Also Sum could be made the three bit XOR of A, B, and C and Carry could be made the three-bit common function of outputs of 1-bit full adder A, B, and C. The expression of Sum and Carry based on binary inputs A, B, C are represented as: inverter circuits for inverting intermediate signals output from the first and second nodes, respectively, to generate complementary signals, wherein each of the first and second inverter circuits is configured as a differential EDMOS logic having an enhancement-type NMOS and depletion-type NMOS serially connected between ground potential and supply potential, the conduction states of the enhancement-type and depletion-type NMOSs being differentially controlled by complementary signals. II. EXISTING SYSTEM DESIGN A. For Sum logic Fig. 1.2 B. For Carry logic Fig. 1.3 In this system there is a spectrum sensing technique based on MRFB, which can have variable sensing resolutions and can adapt to different sensing bandwidths by software reconfiguration. MRFB-based spectrum sensor is
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  Implementation of FullAdder Cell Using High Performance CMOS Technology (IJSRD/Vol. 2/Issue 07/2014/061) All rights reserved by www.ijsrd.com 264 having a gate count reduction. In existing paper they present an exploratory study of popular adder structures implemented in the IBM 90-nm process and analyzed for fan-in, fan-out, and process variations. The adders selected for this study included the standard transistor full adder, mirror adder, multiplexer- based adder, transmission gate-based adder, hybrid full adder, and majority full adder. Each of the adders was also classified according to the logic function realized. Using this approach they presented an analysis of the possible impact of logic function choice and not just circuit choice on the performance of the final adder. III. PROPOSED SYSTEM DESIGN A. Full adder design includes both sum and carry using CMOS Technology Fig. 1.4 The main objective of the proposed work is:- In proposed system the design in terms of both speed and energy consumption becomes even more significant as the world length of the adder increases. To reduce power consumption, approximate implementations of a circuit have been considered as a solution for application in which strict exactness is required. In this power reduction is achieved through the relaxation of the often demanding requirement of accuracy. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. We are designing this circuit using ripple carry adder technique. By this method we are facing problems related to propagation delay. The major problem in ripple carry adder regarding the propagation delay for full-adder is that it is necessary to obtain an intermediate signal and its complement, which are then used to drive other blocks to generate the final outputs. So in this existing method we are using ripple carry adder technique by which delay is more and speed is less. In this design we are using one control signal for calculating sum and carry. So, our output for this circuit depends on control which makes this design more complex. If circuit design is more complex then it will consume more area and if area will be more then power consumption will increase and at the same time speed will reduce. IV. SIMULATION RESULTS A. Schematic design includes both Sum and Carry logic Fig. 1.5 B. Layout design for the proposed method Fig. 1.6 Simulation waveforms for different parameters are shown below: In figure below shows the simulation waveforms for voltage with respect to the time. By simulation result can compare the power consumption for the design with conventional method. Fig. 1.7: Voltage vs Time Fig. 1.8 shows the simulation waveforms for Voltage vs Current Fig. 1.8: Voltage vs Current
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  Implementation of FullAdder Cell Using High Performance CMOS Technology (IJSRD/Vol. 2/Issue 07/2014/061) All rights reserved by www.ijsrd.com 265 Fig. 1.9 shows the simulation waveforms for Voltages vs voltage Fig. 1.9: Voltages vs voltage Fig. 1.10 shows the simulation waveforms for frequency and time graph. Fig. 1.10 Frequency vs Time Characteristics parameters Existing system(power consumption) Proposed system(power consumption) Voltage Vs Time 0.139mw 30.798microW Voltages and Current 0.155mW 29.942 micro W Voltage Vs Voltage 0.139mW 29.942micoW Frequency Vs Time 0.154mW 29.728microW Table 1: comparison table V. CONCLUSION AND FUTURE WORK It has been shown that reducing the supply voltage is the most direct means of reducing dissipated power and operating CMOS devices is considered to be the most energy-efficient solution for low-performance applications. In proposed system the power consumption is reduced to about 100 microwatt which is about 35% as compared to the existing system. With the increasing demand for battery- operated portable applications such as cell phones, PDAs and laptop computers, as well as low-intensity applications such as distributed sensor networks, the need for power sensitive design has grown significantly. So for future work we can further change the design to get minimal power. ACKNOWLEDGEMENT I am highly grateful to Mrs. Ankita Aggarwal Assistant Professor at, GGGI for giving me invaluable guidance in the field of VLSI and providing me the opportunity to carry out this work further. It was the essential encouragement that enables me to pursue my work in this field. REFERENCES [1] Purohit, S. , Margala, M.Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Pages:1327 - 1331 ,Volume:20, Issue: 7 ) July 2012 . [2] Mugilvannan, L.; Ramasamy, S. "Low-power and area-efficient carry select adder using modified BEC- 1 converter", Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on, On page(s): 1 - 5 [3] Singh, R.; Akashe, S. "New high performance low power 4 bit full adder with reduce ground bounce noise", Advanced Electronic Systems (ICAES), 2013 International Conference on, On page(s): 346 – 349 [4] Purohit, S.S.; Chalamalasetti, S.R.; Margala, M.; Vanderbauwhede, W.A. "Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, On page(s): 1915 - 1927 Volume: 21, Issue: 10, Oct. 2013 [5] Khatibzadeh, A.A.; Raahemifar, K. "A 14-transistor low power high-speed full adder cell", Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on, On page(s): 163 - 166 vol.1 Volume: 1, 4-7 May 2003 [6] Shoarinejad, A.; Ung, S.A.; Badawy, W. "Low-power single-bit full adder cells", Electrical and Computer Engineering, Canadian Journal of, On page(s): 3 - 9 Volume: 28, Issue: 1, January 2003 [7] Gupta, J.; Grover, A.; Wadhwa, G.K.; Grover, N. "Multipliers Using Low Power Adder Cells Using 180nm Technology", Computational and Business Intelligence (ISCBI), 2013 International Symposium on, On page(s): 3 – 6 [8] Meher, P.; Mahapatra, K.K. "Low power noise tolerant domino 1-bit full adder", Advances in Energy Conversion Technologies (ICAECT), 2014 International Conference on, On page(s): 125 – 129 [9] Suriya, T.S.U.; Rani, A.A. "Low power analysis of MAC using modified booth algorithm", Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on, On page(s): 1 – 5 [10]More, T.V.; Kshirsagar, R.V. "Design of low power column bypass multiplier using FPGA", Electronics Computer Technology (ICECT), 2011 3rd International Conference on, On page(s): 431 - 435 Volume: 3, 8-10 April 2011 [11]Pieper, L.Z.; da Costa, E.A.C.; Monteiro, J.C. "Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers", Integrated Circuits and Systems Design (SBCCI), 2013 26th Symposium on, On page(s): 1 – 6 [12]Prabhu, A.S.; Elakya, V. "Design of modified low power booth multiplier", Computing, Communication and Applications (ICCCA), 2012 International Conference on, On page(s): 1 - 6
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  Implementation of FullAdder Cell Using High Performance CMOS Technology (IJSRD/Vol. 2/Issue 07/2014/061) All rights reserved by www.ijsrd.com 266 [13]Shubin, V.V. "Analysis and comparison of ripple carry full adders by speed", Micro/Nanotechnologies and Electron Devices (EDM), 2010 International Conference and Seminar on, On page(s): 132 - [14]I. S. Abu-Khater, R. H. Yan, A. Bellaouar, and M. I. Elmasry, "A 1-V low-power high-performance 32-bit conditional sum adder", 1994 IEEE Symp. Low Power Electron., pp.66 -67 1994.