The 8051 microcontroller and embedded systems using assembly and c 2nd-ed

The 8051 Microcontroller and Embedded
Systems
Using Assembly and C
Second Edition

Muhammad Ali Mazidi
Janice Gillispie Mazidi
Rolin D. McKinlay

CONTENTS

Introduction to Computing
The 8051 Microcontrollers
8051 Assembly Language Programming
Branch Instructions
I/O Port Programming
8051 Addressing Modes
Arithmetic & Logic Instructions And Programs
8051 Programming in C
8051 Hardware Connection and Hex File
8051 Timer/Counter Programming in Assembly and C
8051 Serial Port Programming in Assembly and C
Interrupts Programming in Assembly and C
8051 Interfacing to External Memory
8051 Real World Interfacing I: LCD,ADC AND
SENSORS
LCD and Keyboard Interfacing
8051 Interfacing with 8255

INTRODUCTION TO
COMPUTING

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab
Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN

Numbering and coding systems
OUTLINES
Digital primer
Inside the computer

Department of Computer Science and Information Engineering
HANEL National Cheng Kung University, TAIWAN 2

Human beings use base 10 (decimal)
NUMBERING
AND CODING
arithmetic
SYSTEMS There are 10 distinct symbols, 0, 1, 2, …,
9
Decimal and Computers use base 2 (binary) system
Binary Number There are only 0 and 1
Systems
These two binary digits are commonly
referred to as bits


Divide the decimal number by 2
NUMBERING
AND CODING
repeatedly
SYSTEMS Keep track of the remainders
Continue this process until the quotient
Converting becomes zero
from Decimal
Write the remainders in reverse order
to Binary
to obtain the binary number
Ex. Convert 2510 to binary
Quotient Remainder
25/2 = 12 1 LSB (least significant bit)
12/2 = 6 0
6/2 = 3 0
3/2 = 1 1
1/2 = 0 1 MSB (most significant bit)
Therefore 2510 = 110012

Know the weight of each bit in a binary
NUMBERING number
AND CODING
Add them together to get its decimal
SYSTEMS
equivalent
Converting Ex. Convert 110012 to decimal
from Binary to Weight: 24 23 22 21 20
Decimal Digits: 1 1 0 0 1
Sum: 16 + 8+ 0+ 0+ 1 = 2510

Use the concept of weight to convert a
decimal number to a binary directly
Ex. Convert 3910 to binary
32 + 0 + 0 + 4 + 2 + 1 = 39
Therefore, 3910 = 1001112

Base 16, the
NUMBERING
AND CODING
hexadecimal system, Decimal Binary Hex

SYSTEMS is used as a 0 0000 0
1 0001 1
convenient 2 0010 2
Hexadecimal representation of 3 0011 3
4 0100 4
System binary numbers 5 0101 5
ex. 6 0110 6
7 0111 7
It is much easier to 8 1000 8
represent a string of 0s 9 1001 9
and 1s such as 10 1010 A
100010010110 as its 11 1011 B
hexadecimal equivalent of 12 1100 C
896H 13 1101 D
14 1110 E
15 1111 F


To represent a binary number as its
NUMBERING equivalent hexadecimal number
AND CODING
Start from the right and group 4 bits at a
SYSTEMS
time, replacing each 4-bit binary number
with its hex equivalent
Converting
between Binary Ex. Represent binary 100111110101 in hex
and Hex 1001 1111 0101
= 9 F 5

To convert from hex to binary
Each hex digit is replaced with its 4-bit
binary equivalent
Ex. Convert hex 29B to binary
2 9 B
= 0010 1001 1011

Convert to binary first and then
NUMBERING
AND CODING
convert to hex
SYSTEMS Convert directly from decimal to hex
by repeated division, keeping track of
Converting the remainders
from Decimal
to Hex Ex. Convert 4510 to hex
32 16 8 4 2 1
1 0 1 1 0 1 32 + 8 + 4 + 1 = 45
4510 = 0010 11012 = 2D16
Ex. Convert 62910 to hex
512 256 128 64 32 16 8 4 2 1
1 0 0 1 1 1 0 1 0 1
62910 = 512+64+32+16+4+1 = 0010 0111 01012 = 27516


Convert from hex to binary and then to
NUMBERING
AND CODING
decimal
SYSTEMS Convert directly from hex to decimal
by summing the weight of all digits
Converting
from Hex to Ex. 6B216 = 0110 1011 00102
1024 512 256 128 64 32 16 8 4 2 1
Decimal
1 1 0 1 0 1 1 0 0 1 0
1024 + 512 + 128 + 32 + 16 + 2 = 171410


Adding the digits together from the
NUMBERING
AND CODING
least significant digits
SYSTEMS If the result is less than 16, write that digit
as the sum for that position
Addition of Hex If it is greater than 16, subtract 16 from it
Numbers to get the digit and carry 1 to the next
digit
Ex. Perform hex addition: 23D9 + 94BE

23D9 LSD: 9 + 14 = 23 23 – 16 = 7 w/ carry
+ 94BE 1 + 13 + 11 = 25 25 – 16 = 9 w/ carry
B897 1 + 3+4=8
MSD: 2 + 9=B


If the second digit is greater than the
NUMBERING
AND CODING
first, borrow 16 from the preceding
SYSTEMS digit
Ex. Perform hex subtraction: 59F – 2B8
Subtraction of
Hex Numbers 59F LSD: 15 – 8 = 7
– 2B8 9 + 16 – 11 = 14 = E16
2E7 5–1–2=2


The ASCII (pronounced “ask-E”) code
NUMBERING assigns binary patterns for
AND CODING Numbers 0 to 9
SYSTEMS All the letters of English alphabet,
uppercase and lowercase
ASCII Code Many control codes and punctuation
marks
The ASCII system uses 7 bits to
represent each code
Hex Symbol Hex Symbol
Selected ASCII codes 41 A 61 a
42 B 62 b
43 C 63 c
44 D 64 d
... ... ... …
59 Y 79 y
5A Z 7A z

Two voltage levels can be represented
DIGITAL
PRIMER
as the two digits 0 and 1
Signals in digital electronics have two
Binary Logic distinct voltage levels with built-in
tolerances for variations in the voltage
A valid digital signal should be within
either of the two shaded areas
5
4 Logic 1
3
2
1
Logic 0
0


AND gate
DIGITAL
PRIMER

Logic Gates

Computer Science Illuminated, Dale and Lewis

OR gate



Tri-state buffer
DIGITAL
PRIMER Inverter

Logic Gates
(cont’)


XOR gate



NAND gate
DIGITAL
PRIMER

Logic Gates
(cont’)

NOR gate



DIGITAL
PRIMER Half adder

Logic Design
Using Gates

Full adder

Digital Design, Mano


DIGITAL
PRIMER
4-bit adder
Logic Design
Using Gates
(cont’)



Decoders
DIGITAL
PRIMER Decoders are widely used for address
decoding in computer design
Logic Design Address Decoders
Using Gates
(cont’)

Address decoder for 9 (10012) Address decoder for 5 (01012)
The output will be 1 if and The output will be 1 if and
only if the input is 10012 only if the input is 01012


Flip-flops
DIGITAL
PRIMER Flip-flops are frequently used to store data

Logic Design
Using Gates
(cont’)


The unit of data size
INSIDE THE
COMPUTER Bit : a binary digit that can have the value
0 or 1
Important Byte : 8 bits
Terminology Nibble : half of a bye, or 4 bits
Word : two bytes, or 16 bits
The terms used to describe amounts of
memory in IBM PCs and compatibles
Kilobyte (K): 210 bytes
Megabyte (M) : 220 bytes, over 1 million
Gigabyte (G) : 230 bytes, over 1 billion
Terabyte (T) : 240 bytes, over 1 trillion


CPU (Central Processing Unit)
INSIDE THE Execute information stored in memory
COMPUTER I/O (Input/output) devices
Provide a means of communicating with
Internal CPU
Organization of Memory
Computers RAM (Random Access Memory) –
temporary storage of programs that
computer is running
The data is lost when computer is off
ROM (Read Only Memory) – contains
programs and information essential to
operation of the computer
The information cannot be changed by use,
and is not lost when power is off
– It is called nonvolatile memory


INSIDE THE
COMPUTER

Internal Address bus
Organization of
Computers Memory
Peripherals
(cont’) CPU (monitor,
(RAM, ROM)
printer, etc.)

Data bus


The CPU is connected to memory and
INSIDE THE
COMPUTER
I/O through strips of wire called a bus
Carries information from place to place
Internal Address bus
Organization of Data bus
Control bus
Computers
(cont’)
Address bus

RAM ROM Printer Disk Monitor Keyboard
CPU

Data bus
Read/
Write
Control bus


Address bus
INSIDE THE
For a device (memory or I/O) to be
COMPUTER recognized by the CPU, it must be
assigned an address
Internal The address assigned to a given device must
Organization of be unique
Computers The CPU puts the address on the address bus,
(cont’) and the decoding circuitry finds the device
Data bus
The CPU either gets data from the device
or sends data to it
Control bus
Provides read or write signals to the
device to indicate if the CPU is asking for
information or sending it information


The more data buses available, the
INSIDE THE
COMPUTER
better the CPU
Think of data buses as highway lanes
More about More data buses mean a more
Data Bus expensive CPU and computer
The average size of data buses in CPUs
varies between 8 and 64
Data buses are bidirectional
To receive or send data
The processing power of a computer is
related to the size of its buses


The more address buses available, the
INSIDE THE larger the number of devices that can
COMPUTER be addressed
More about The number of locations with which a
Address Bus CPU can communicate is always equal
to 2x, where x is the address lines,
regardless of the size of the data bus
ex. a CPU with 24 address lines and 16
data lines can provide a total of 224 or 16M
bytes of addressable memory
Each location can have a maximum of 1
byte of data, since all general-purpose
CPUs are byte addressable
The address bus is unidirectional


For the CPU to process information,
INSIDE THE the data must be stored in RAM or
COMPUTER ROM, which are referred to as primary
memory
CPU’s Relation ROM provides information that is fixed
to RAM and and permanent
ROM Tables or initialization program
RAM stores information that is not
permanent and can change with time
Various versions of OS and application
packages
CPU gets information to be processed
first form RAM (or ROM)
if it is not there, then seeks it from a mass
storage device, called secondary memory, and
transfers the information to RAM


Registers
INSIDE THE
COMPUTER The CPU uses registers to store
information temporarily
Inside CPUs Values to be processed
Address of value to be fetched from memory
In general, the more and bigger the
registers, the better the CPU
Registers can be 8-, 16-, 32-, or 64-bit
The disadvantage of more and bigger registers
is the increased cost of such a CPU


Address Bus
INSIDE THE
COMPUTER Program Counter

Inside CPUs
(cont’)
Instruction Register

Control Bus Data Bus
Flags ALU
Instruction decoder,
timing, and control

Internal Register A
buses
Register B
Register C
Register D


ALU (arithmetic/logic unit)
INSIDE THE
Performs arithmetic functions such as add,
COMPUTER subtract, multiply, and divide, and logic
functions such as AND, OR, and NOT
Inside CPUs
(cont’)
Program counter
Points to the address of the next
instruction to be executed
As each instruction is executed, the program
counter is incremented to point to the address
of the next instruction to be executed
Instruction decoder
Interprets the instruction fetched into the
CPU
A CPU capable of understanding more
instructions requires more transistors to design


Ex. A CPU has registers A, B, C, and D and it has an 8-bit
INSIDE THE data bus and a 16-bit address bus. The CPU can access
COMPUTER memory from addresses 0000 to FFFFH
Assume that the code for the CPU to move a value to
Internal register A is B0H and the code for adding a value to
Working of register A is 04H
Computers The action to be performed by the CPU is to put 21H into
register A, and then add to register A values 42H and 12H

...


Ex. (cont’)
INSIDE THE Action Code Data
COMPUTER Move value 21H into reg. A B0H 21H
Add value 42H to reg. A 04H 42H
Internal Add value 12H to reg. A 04H 12H
Working of
Mem. addr. Contents of memory address
Computers 1400 (B0) code for moving a value to register A
(cont’) 1401 (21) value to be moved
1402 (04) code for adding a value to register A
1403 (42) value to be added
1404 (04) code for adding a value to register A
1405 (12) value to be added
1406 (F4) code for halt

...


Ex. (cont’)
INSIDE THE The actions performed by CPU are as follows:
COMPUTER 1. The program counter is set to the value 1400H,
indicating the address of the first instruction code to
Internal be executed
Working of 2.
Computers The CPU puts 1400H on address bus and sends it
(cont’) out
The memory circuitry finds the location
The CPU activates the READ signal, indicating to
memory that it wants the byte at location 1400H
以動畫表示 This causes the contents of memory location
1400H, which is B0, to be put on the data bus and
brought into the CPU
...


Ex. (cont’)
INSIDE THE 3.
COMPUTER The CPU decodes the instruction B0
The CPU commands its controller circuitry to bring
Internal into register A of the CPU the byte in the next
Working of memory location
Computers The value 21H goes into register A
(cont’) The program counter points to the address of the
next instruction to be executed, which is 1402H
Address 1402 is sent out on the address bus to
fetch the next instruction

...


Ex. (cont’)
INSIDE THE 4.
COMPUTER From memory location 1402H it fetches code 04H
After decoding, the CPU knows that it must add to
Internal the contents of register A the byte sitting at the
Working of next address (1403)
Computers After the CPU brings the value (42H), it provides
(cont’) the contents of register A along with this value to
the ALU to perform the addition
It then takes the result of the addition from the
ALU’s output and puts it in register A
The program counter becomes 1404, the address
of the next instruction

...


Ex. (cont’)
INSIDE THE 5.
COMPUTER Address 1404H is put on the address bus and the
code is fetched into the CPU, decoded, and
Internal executed
Working of This code is again adding a value to register A
Computers The program counter is updated to 1406H
(cont’) 6.
The contents of address 1406 are fetched in and
executed
This HALT instruction tells the CPU to stop
incrementing the program counter and asking for
the next instruction


8051 MICROCONTROLLERS


Chung-Ping Young
楊中平


Microcontrollers and embedded
OUTLINES
processors
Overview of the 8051 family


General-purpose microprocessors
MICRO-
CONTROLLERS
contains
AND No RAM
EMBEDDED No ROM
PROCESSORS No I/O ports

Microcontroller
Microcontroller has
vs. General- CPU (microprocessor)
Purpose RAM
Microprocessor ROM
I/O ports
Timer
ADC and other peripherals


Data bus
MICRO- General-
purpose
CONTROLLERS Micro-
Processor I/O Serial
AND RAM ROM
Port
Timer COM
Port
EMBEDDED
PROCESSORS CPU
Address bus

Microcontroller

For Evaluation Only.
Copyright(C) by Foxit Software Company,2005-2008
Edited by Foxit Reader
vs. General-
Purpose Microcontroller
Microprocessor CPU RAM ROM
(cont’)

Serial
I/O Timer COM
Port


General-purpose microprocessors
MICRO-
Must add RAM, ROM, I/O ports, and
CONTROLLERS timers externally to make them functional
AND Make the system bulkier and much more
EMBEDDED expensive
PROCESSORS Have the advantage of versatility on the
amount of RAM, ROM, and I/O ports
Microcontroller Microcontroller
vs. General- The fixed amount of on-chip ROM, RAM,
Purpose and number of I/O ports makes them ideal
Microprocessor for many applications in which cost and
(cont’) space are critical
In many applications, the space it takes,
the power it consumes, and the price per
unit are much more critical considerations
than the computing power


An embedded product uses a
MICRO- microprocessor (or microcontroller) to
CONTROLLERS do one task and one task only
AND
There is only one application software that
EMBEDDED
is typically burned into ROM
PROCESSORS
A PC, in contrast with the embedded
Microcontrollers system, can be used for any number of
for Embedded applications
Systems It has RAM memory and an operating
system that loads a variety of applications
into RAM and lets the CPU run them
A PC contains or is connected to various
embedded products
Each one peripheral has a microcontroller inside
it that performs only one task


Home
MICRO- Appliances, intercom, telephones, security systems,
CONTROLLERS garage door openers, answering machines, fax
AND machines, home computers, TVs, cable TV tuner,
VCR, camcorder, remote controls, video games,
EMBEDDED cellular phones, musical instruments, sewing
PROCESSORS machines, lighting control, paging, camera, pinball
machines, toys, exercise equipment
Microcontrollers Office
for Embedded Telephones, computers, security systems, fax
Systems machines, microwave, copier, laser printer, color
printer, paging
(cont’)
Auto
Trip computer, engine control, air bag, ABS,
instrumentation, security system, transmission
control, entertainment, climate control, cellular
phone, keyless entry


Many manufactures of general-purpose
MICRO- microprocessors have targeted their
CONTROLLERS microprocessor for the high end of the
AND
embedded market
EMBEDDED
There are times that a microcontroller is
PROCESSORS
inadequate for the task
x86 PC When a company targets a general-
Embedded purpose microprocessor for the
Applications embedded market, it optimizes the
processor used for embedded systems
Very often the terms embedded
processor and microcontroller are used
interchangeably


One of the most critical needs of an
MICRO- embedded system is to decrease
CONTROLLERS power consumption and space
AND
EMBEDDED In high-performance embedded
PROCESSORS processors, the trend is to integrate
more functions on the CPU chip and let
x86 PC designer decide which features he/she
Embedded wants to use
Applications In many cases using x86 PCs for the
(cont’)
high-end embedded applications
Saves money and shortens development
time
A vast library of software already written
Windows is a widely used and well understood
platform

8-bit microcontrollers
MICRO-
CONTROLLERS Motorola’s 6811
AND Intel’s 8051
EMBEDDED Zilog’s Z8
PROCESSORS Microchip’s PIC

Choosing a There are also 16-bit and 32-bit
Microcontroller microcontrollers made by various chip
makers


Meeting the computing needs of the
MICRO-
CONTROLLERS
task at hand efficiently and cost
AND effectively
EMBEDDED Speed
PROCESSORS Packaging
Power consumption
Criteria for
The amount of RAM and ROM on chip
Choosing a
Microcontroller The number of I/O pins and the timer on
chip
How easy to upgrade to higher-
performance or lower power-consumption
versions
Cost per unit


Availability of software development
MICRO- tools, such as compilers, assemblers,
CONTROLLERS and debuggers
AND
EMBEDDED Wide availability and reliable sources
PROCESSORS of the microcontroller
The 8051 family has the largest number of
Criteria for diversified (multiple source) suppliers
Intel (original)

Choosing a
Atmel
Microcontroller
(cont’) Philips/Signetics
AMD
Infineon (formerly Siemens)
Matra
Dallas Semiconductor/Maxim


Intel introduced 8051, referred as MCS-
OVERVIEW OF 51, in 1981
8051 FAMILY The 8051 is an 8-bit processor
The CPU can work on only 8 bits of data at a
time
8051
Microcontroller The 8051 had
128 bytes of RAM
4K bytes of on-chip ROM
Two timers

One serial port
Four I/O ports, each 8 bits wide
6 interrupt sources
The 8051 became widely popular after
allowing other manufactures to make
and market any flavor of the 8051, but
remaining code-compatible

External
Interrupts
OVERVIEW OF
8051 FAMILY

Counter Inputs
On-chip
Interrupt ROM On-chip Etc.
Control Timer 0
8051 for code RAM Timer 1
Microcontroller
(cont’)
CPU

OSC Bus I/O Serial
Control Ports Port

P0 P1 P2 P3 TXD RXD

Address/Data


The 8051 is a subset of the 8052
OVERVIEW OF
8051 FAMILY The 8031 is a ROM-less 8051
Add external ROM to it
8051 Family You lose two ports, and leave only 2 ports
for I/O operations

Feature 8051 8052 8031
ROM (on-chip program
4K 8K 0K
space in bytes)
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6


8751 microcontroller
OVERVIEW OF
8051 FAMILY UV-EPROM
PROM burner
Various 8051 UV-EPROM eraser takes 20 min to erase
Microcontrollers AT89C51 from Atmel Corporation
Flash (erase before write)
ROM burner that supports flash

A separate eraser is not needed
DS89C4x0 from Dallas Semiconductor,
now part of Maxim Corp.
Flash
Comes with on-chip loader, loading program to
on-chip flash via PC COM port


DS5000 from Dallas Semiconductor
OVERVIEW OF
8051 FAMILY NV-RAM (changed one byte at a time),
RTC (real-time clock)
Various 8051 Also comes with on-chip loader
Microcontrollers OTP (one-time-programmable) version
(cont’) of 8051
8051 family from Philips
ADC, DAC, extended I/O, and both OTP
and flash


8051 ASSEMBLY
LANGUAGE
PROGRAMMING


Chung-Ping Young
楊中平


Register are used to store information
INSIDE THE
8051
temporarily, while the information
could be
Registers a byte of data to be processed, or
an address pointing to the data to be
fetched
The vast majority of 8051 register are
8-bit registers
There is only one data type, 8 bits


The 8 bits of a register are shown from
INSIDE THE
8051
MSB D7 to the LSB D0
With an 8-bit data type, any data larger
Registers than 8 bits must be broken into 8-bit
(cont’) chunks before it is processed
most least
significant bit significant bit

D7 D6 D5 D4 D3 D2 D1 D0

8 bit Registers


The most widely used registers
INSIDE THE
8051 A (Accumulator)
For all arithmetic and logic instructions
Registers B, R0, R1, R2, R3, R4, R5, R6, R7
(cont’) DPTR (data pointer), and PC (program
counter)
A

B
R0 DPTR DPH DPL
R1
R2
PC PC (Program counter)
R3
R4
R5
R6
R7


MOV destination, source ;copy source to dest.
INSIDE THE The instruction tells the CPU to move (in reality,
8051 COPY) the source operand to the destination
operand
MOV “#” signifies that it is a value
Instruction
MOV A,#55H ;load value 55H into reg. A
MOV R0,A ;copy contents of A into R0
;(now A=R0=55H)
;(now A=R0=R1=55H)
;(now A=R0=R1=R2=55H)
MOV R3,#95H ;load value 95H into R3
;(now R3=95H)
MOV A,R3 ;copy contents of R3 into A
;now A=R3=95H


Notes on programming
INSIDE THE Value (proceeded with #) can be loaded
8051 directly to registers A, B, or R0 – R7
MOV A, #23H
MOV MOV R5, #0F9H If it’s not preceded with #,
Instruction Add a 0 to indicate that
it means to load from a
memory location
(cont’) F is a hex number and
not a letter

If values 0 to F moved into an 8-bit
register, the rest of the bits are assumed
all zeros
“MOV A, #5”, the result will be A=05; i.e., A
= 00000101 in binary
Moving a value that is too large into a
register will cause an error
MOV A, #7F2H ; ILLEGAL: 7F2H>8 bits (FFH)

ADD A, source ;ADD the source operand
INSIDE THE ;to the accumulator
8051 The ADD instruction tells the CPU to add the source
byte to register A and put the result in register A
ADD Source operand can be either a register or
immediate data, but the destination must always
Instruction be register A
“ADD R4, A” and “ADD R2, #12H” are invalid
since A must be the destination of any arithmetic
operation
MOV A, #25H ;load 25H into A
MOV R2, #34H ;load 34H into R2
ADD A, R2 ;add R2 to Accumulator
There are always ;(A = A + R2)
many ways to write
the same program, MOV A, #25H ;load one operand
depending on the ;into A (A=25H)
registers used ADD A, #34H ;add the second
;operand 34H to A

In the early days of the computer,
8051 programmers coded in machine language,
ASSEMBLY consisting of 0s and 1s
PROGRAMMING Tedious, slow and prone to error
Assembly languages, which provided
Structure of
mnemonics for the machine code instructions,
Assembly
plus other features, were developed
Language
An Assembly language program consist of a series
of lines of Assembly language instructions
Assembly language is referred to as a low-
level language
It deals directly with the internal structure of the
CPU


Assembly language instruction includes
8051 a mnemonic (abbreviation easy to remember)
ASSEMBLY the commands to the CPU, telling it what those
PROGRAMMING to do with those items
optionally followed by one or two operands
Structure of the data items being manipulated
Assembly
A given Assembly language program is
Language
a series of statements, or lines

Assembly language instructions
Tell the CPU what to do
Directives (or pseudo-instructions)
Give directions to the assembler


An Assembly language instruction
8051
ASSEMBLY consists of four fields:
PROGRAMMING [label:] Mnemonic [operands] [;comment]

ORG 0H ;start(origin) at location
Structure of 0
MOV R5, #25H ;load 25H into R5
Assembly MOV R7, #34H ;load 34H into R7 Directives do not
Language MOV A, #0 ;load 0 into generate any machine
A
ADD A, R5 ;add contents ofand are used
code R5 to A
;now A = A + only by the assembler
R5
Mnemonics ADD A, R7 ;add contents of R7 to A
produce ;now A = A + R7
opcodes ADD A, #12H ;add to A value 12H
;now A = A + 12H
HERE: SJMP HERE ;stay in this loop
END ;end of asm may be at the end of a
Comments source file
The label field allows line or on a line by themselves
the program to refer to a The assembler ignores comments
line of code by name

The step of Assembly language
ASSEMBLING
AND RUNNING
program are outlines as follows:
AN 8051 1) First we use an editor to type a program,
PROGRAM many excellent editors or word
processors are available that can be used
to create and/or edit the program
Notice that the editor must be able to produce
an ASCII file
For many assemblers, the file names follow
the usual DOS conventions, but the source file
has the extension “asm“ or “src”, depending
on which assembly you are using


2) The “asm” source file containing the
ASSEMBLING program code created in step 1 is fed to
AND RUNNING an 8051 assembler
AN 8051 The assembler converts the instructions into
PROGRAM machine code
(cont’) The assembler will produce an object file and
a list file
The extension for the object file is “obj” while
the extension for the list file is “lst”
3) Assembler require a third step called
linking
The linker program takes one or more object
code files and produce an absolute object file
with the extension “abs”
This abs file is used by 8051 trainers that
have a monitor program


4) Next the “abs” file is fed into a program
ASSEMBLING called “OH” (object to hex converter)
AND RUNNING which creates a file with extension “hex”
AN 8051 that is ready to burn into ROM
PROGRAM This program comes with all 8051 assemblers
(cont’)
Recent Windows-based assemblers combine
step 2 through 4 into one step


EDITOR
PROGRAM
ASSEMBLING myfile.asm
AND RUNNING
AN 8051 ASSEMBLER
PROGRAM PROGRAM
myfile.lst
Other obj files
Steps to Create myfile.obj

a Program LINKER
PROGRAM

myfile.abs

OH
PROGRAM

myfile.hex

The lst (list) file, which is optional, is
ASSEMBLING
AND RUNNING
very useful to the programmer
AN 8051 It lists all the opcodes and addresses as
PROGRAM well as errors that the assembler detected
The programmer uses the lst file to find
lst File the syntax errors or debug
1 0000 ORG 0H ;start (origin) at 0
2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A
;now A = A + R5
6 0007 2F ADD A,R7 ;add contents of R7 to A
;now A = A + R7
7 0008 2412 ADD A,#12H ;add to A value 12H
;now A = A + 12H
8 000A 80EF HERE: SJMP HERE;stay in this loop
9 000C END ;end of asm source file
address

The program counter points to the
PROGRAM
COUNTER AND
address of the next instruction to be
ROM SPACE executed
As the CPU fetches the opcode from the
Program program ROM, the program counter is
Counter increasing to point to the next instruction
The program counter is 16 bits wide
This means that it can access program
addresses 0000 to FFFFH, a total of 64K
bytes of code


All 8051 members start at memory
PROGRAM
COUNTER AND
address 0000 when they’re powered
ROM SPACE up
Program Counter has the value of 0000
Power up The first opcode is burned into ROM
address 0000H, since this is where the
8051 looks for the first instruction when it

is booted
We achieve this by the ORG statement in
the source program


Examine the list file and how the code
PROGRAM is placed in ROM
COUNTER AND 1 0000 ORG 0H ;start (origin) at 0

ROM SPACE
2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A
Placing Code in ;now A = A + R5
6 0007 2F ADD A,R7 ;add contents of R7 to A
ROM ;now A = A + R7
7 0008 2412 ADD A,#12H ;add to A value 12H
;now A = A + 12H
8 000A 80EF HERE: SJMP HERE ;stay in this loop
9 000C END ;end of asm source file

ROM Address Machine Language Assembly Language
0000 7D25 MOV R5, #25H
0002 7F34 MOV R7, #34H
0004 7400 MOV A, #0
0006 2D ADD A, R5
0007 2F ADD A, R7
0008 2412 ADD A, #12H
000A 80EF HERE: SJMP HERE


After the program is burned into ROM,
PROGRAM
COUNTER AND
the opcode and operand are placed in
ROM SPACE ROM memory location starting at 0000
ROM contents
Address Code
Placing Code in
0000 7D
ROM 0001 25
(cont’) 0002 7F
0003 34
0004 74
0005 00
0006 2D
0007 2F
0008 24
0009 12
000A 80
000B FE


A step-by-step description of the
PROGRAM
COUNTER AND
action of the 8051 upon applying
ROM SPACE power on it
1. When 8051 is powered up, the PC has
Executing 0000 and starts to fetch the first opcode
Program from location 0000 of program ROM
Upon executing the opcode 7D, the CPU
fetches the value 25 and places it in R5
Now one instruction is finished, and then the
PC is incremented to point to 0002, containing
opcode 7F
2. Upon executing the opcode 7F, the value
34H is moved into R7
The PC is incremented to 0004


(cont’)
PROGRAM
COUNTER AND 3. The instruction at location 0004 is
ROM SPACE executed and now PC = 0006
4. After the execution of the 1-byte
Executing instruction at location 0006, PC = 0007
Program 5. Upon execution of this 1-byte instruction
(cont’) at 0007, PC is incremented to 0008

This process goes on until all the instructions
are fetched and executed
The fact that program counter points at the
next instruction to be executed explains some
microprocessors call it the instruction pointer


No member of 8051 family can access
PROGRAM
COUNTER AND
more than 64K bytes of opcode
ROM SPACE The program counter is a 16-bit register

ROM Memory Byte Byte Byte

Map in 8051 0000 0000 0000

Family
0FFF
8751
AT89C51 3FFF
DS89C420/30

7FFF
DS5000-32


8051 microcontroller has only one data
8051 DATA
TYPES AND
type - 8 bits
DIRECTIVES The size of each register is also 8 bits
It is the job of the programmer to break
Data Type down data larger than 8 bits (00 to FFH,
or 0 to 255 in decimal)
The data types can be positive or negative


The DB directive is the most widely
8051 DATA
TYPES AND
used data directive in the assembler
DIRECTIVES It is used to define the 8-bit data
When DB is used to define data, the
Assembler numbers can be in decimal, binary, hex,
The “D” after the decimal
Directives ASCII formats number is optional, but using
“B” (binary) and “H”
(hexadecimal) for the others is

ORG 500H
required
DATA1: DB 28 ;DECIMAL (1C in Hex)
DATA2: DB 00110101B ;BINARY (35 in Hex)
DATA3: DB 39H ;HEX
The Assembler will ORG 510H Place ASCII in quotation marks
convert the numbers DATA4: DB “2591” The;ASCII NUMBERS ASCII
Assembler will assign
into hex code for the numbers or characters
ORG 518H
DATA6: DB “My name is Joe”
Define ASCII strings larger ;ASCII CHARACTERS
than two characters


ORG (origin)
8051 DATA The ORG directive is used to indicate the
TYPES AND beginning of the address
DIRECTIVES The number that comes after ORG can be
either in hex and decimal
Assembler If the number is not followed by H, it is decimal
Directives and the assembler will convert it to hex
(cont’) END
This indicates to the assembler the end of
the source (asm) file
The END directive is the last line of an
8051 program
Mean that in the code anything after the END
directive is ignored by the assembler


EQU (equate)
8051 DATA
TYPES AND This is used to define a constant without
DIRECTIVES occupying a memory location
The EQU directive does not set aside
Assembler storage for a data item but associates a
directives constant value with a data label
(cont’) When the label appears in the program, its
constant value will be substituted for the label


EQU (equate) (cont’)
8051 DATA
TYPES AND Assume that there is a constant used in
DIRECTIVES many different places in the program, and
the programmer wants to change its value
Assembler throughout
By the use of EQU, one can change it once and
directives
the assembler will change all of its occurrences
(cont’)
Use EQU for the
counter constant

COUNT EQU 25
... ....
MOV R3, #COUNT

The constant is used to
load the R3 register


The program status word (PSW)
FLAG BITS AND
PSW REGISTER
register, also referred to as the flag
register, is an 8 bit register
Program Status Only 6 bits are used
Word These four are CY (carry), AC (auxiliary carry), P
(parity), and OV (overflow)
– They are called conditional flags, meaning
that they indicate some conditions that

resulted after an instruction was executed
The PSW3 and PSW4 are designed as RS0 and
RS1, and are used to change the bank
The two unused bits are user-definable


CY AC F0 RS1 RS0 OV -- P
FLAG BITS AND A carry from D3 to D4
CY PSW.7 Carry flag.
PSW REGISTER
AC PSW.6 Auxiliary carry flag. Carry out from the d7 bit
-- PSW.5 Available to the user for general purpose
Program Status RS1 PSW.4 Register Bank selector bit 1.
Word (cont’) RS0 PSW.3 Register Bank selector bit 0.
OV PSW.2 Overflow flag.
Reflect the number of 1s
The result of -- PSW.1 User definable bit. in register A
signed number P PSW.0 Parity flag. Set/cleared by hardware each
operation is too instruction cycle to indicate an odd/even
large, causing number of 1 bits in the accumulator.
the high-order
bit to overflow RS1 RS0 Register Bank Address
into the sign bit
0 0 0 00H – 07H
0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH


Instructions that affect flag bits
FLAG BITS AND Instruction CY OV AC
PSW REGISTER ADD X X X
ADDC X X X

ADD SUBB X X X
MUL 0 X
Instruction And DIV 0 X
PSW DA X
RPC X
PLC X
SETB C 1
CLR C 0
CPL C X
ANL C, bit X
ANL C, /bit X
ORL C, bit X
ORL C, /bit X
MOV C, bit X
CJNE X


The flag bits affected by the ADD
FLAG BITS AND
PSW REGISTER
instruction are CY, P, AC, and OV
Example 2-2

ADD Show the status of the CY, AC and P flag after the addition of 38H
and 2FH in the following instructions.
Instruction And
PSW MOV A, #38H
(cont’) ADD A, #2FH ;after the addition A=67H, CY=0
Solution:
38 00111000
+ 2F 00101111
67 01100111
CY = 0 since there is no carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 1 since the accumulator has an odd number of 1s (it has five 1s)

Example 2-3
FLAG BITS AND
Show the status of the CY, AC and P flag after the addition of 9CH
PSW REGISTER and 64H in the following instructions.
MOV A, #9CH
ADD ADD A, #64H ;after the addition A=00H, CY=1
Instruction And
Solution:
PSW
(cont’) 9C 10011100
+ 64 01100100
100 00000000
CY = 1 since there is a carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has zero 1s)


Example 2-4
FLAG BITS AND
Show the status of the CY, AC and P flag after the addition of 88H
PSW REGISTER and 93H in the following instructions.
MOV A, #88H
ADD
ADD A, #93H ;after the addition A=1BH, CY=1
Instruction And
PSW Solution:
(cont’) 88 10001000
+ 93 10010011
11B 00011011
CY = 1 since there is a carry beyond the D7 bit
AC = 0 since there is no carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has four 1s)


There are 128 bytes of RAM in the
REGISTER 8051
BANKS AND
Assigned addresses 00 to 7FH
STACK
The 128 bytes are divided into three
RAM Memory different groups as follows:
Space 1) A total of 32 bytes from locations 00 to
Allocation 1F hex are set aside for register banks
and the stack

2) A total of 16 bytes from locations 20H to
2FH are set aside for bit-addressable
read/write memory
3) A total of 80 bytes from locations 30H to
7FH are used for read and write storage,
called scratch pad


RAM Allocation in 8051

8051 7F

REGISTER Scratch pad RAM

BANKS AND 30
STACK 2F
Bit-Addressable RAM

RAM Memory 20
Space 1F
Allocation
Register Bank 3
18
(cont’) 17 Register Bank 2
10
0F
Register Bank 1 (stack)
08
07
Register Bank 0

00


These 32 bytes are divided into 4
8051
REGISTER
banks of registers in which each bank
BANKS AND has 8 registers, R0-R7
STACK RAM location from 0 to 7 are set aside for
bank 0 of R0-R7 where R0 is RAM location
Register Banks 0, R1 is RAM location 1, R2 is RAM
location 2, and so on, until memory
location 7 which belongs to R7 of bank 0
It is much easier to refer to these RAM
locations with names such as R0, R1, and
so on, than by their memory locations
Register bank 0 is the default when
8051 is powered up


8051 Register banks and their RAM address
REGISTER Bank 3
Bank 0 Bank 1 Bank 2
BANKS AND
STACK 7 R7 F R7 17 R7 1F R7

6 R6 E R6 16 R6 1E R6

Register Banks 5 R5 D R5 15 R5 1D R5

(cont’) 4 R4 C R4 14 R4 1C R4

3 R3 B R3 13 R3 1B R3

2 R2 A R2 12 R2 1A R2

1 R1 9 R1 11 R1 19 R1

0 R0 8 R0 10 R0 18 R0


We can switch to other banks by use
8051
REGISTER
of the PSW register
BANKS AND Bits D4 and D3 of the PSW are used to
STACK select the desired register bank
Use the bit-addressable instructions SETB
Register Banks and CLR to access PSW.4 and PSW.3
(cont’)
PSW bank selection
RS1(PSW.4) RS0(PSW.3)
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1


Example 2-5
8051
MOV R0, #99H ;load R0 with 99H
REGISTER MOV R1, #85H ;load R1 with 85H
BANKS AND
STACK
Example 2-6

Register Banks MOV 00, #99H ;RAM location 00H has 99H
MOV 01, #85H ;RAM location 01H has 85H
(cont’)

Example 2-7
SETB PSW.4 ;select bank 2
MOV R0, #99H ;RAM location 10H has 99H
MOV R1, #85H ;RAM location 11H has 85H


The stack is a section of RAM used by
8051 the CPU to store information
REGISTER temporarily
BANKS AND
This information could be data or an
STACK
address
Stack The register used to access the stack
is called the SP (stack pointer) register
The stack pointer in the 8051 is only 8 bit
wide, which means that it can take value
of 00 to FFH
When the 8051 is powered up, the SP
register contains value 07
RAM location 08 is the first location begin used
for the stack by the 8051


The storing of a CPU register in the
8051
stack is called a PUSH
REGISTER
BANKS AND SP is pointing to the last used location of
STACK the stack
As we push data onto the stack, the SP is
Stack incremented by one
(cont’) This is different from many microprocessors

Loading the contents of the stack back
into a CPU register is called a POP
With every pop, the top byte of the stack
is copied to the register specified by the
instruction and the stack pointer is
decremented once


Example 2-8
8051
Show the stack and stack pointer from the following. Assume the
REGISTER default stack area.
BANKS AND MOV R6, #25H
STACK MOV R1, #12H
MOV R4, #0F3H
PUSH 6
Pushing onto PUSH 1
Stack PUSH 4
Solution:
After PUSH 6 After PUSH 1 After PUSH 4
0B 0B 0B 0B
0A 0A 0A 0A F3
09 09 09 12 09 12
08 08 25 08 25 08 25
Start SP = 07 SP = 08 SP = 09 SP = 0A


Example 2-9
8051
Examining the stack, show the contents of the register and SP after
REGISTER execution of the following instructions. All value are in hex.
BANKS AND POP 3 ; POP stack into R3
STACK POP 5 ; POP stack into R5
POP 2 ; POP stack into R2

Popping From Solution:
Stack

After POP 3 After POP 5 After POP 2
0B 54 0B 0B 0B
0A F9 0A F9 0A 0A
09 76 09 76 09 76 09
08 6C 08 6C 08 6C 08 6C
Start SP = 0B SP = 0A SP = 09 SP = 08
Because locations 20-2FH of RAM are reserved
for bit-addressable memory, so we can change the
SP to other RAM location by using the instruction
“MOV SP, #XX”

The CPU also uses the stack to save
8051
REGISTER
the address of the instruction just
BANKS AND below the CALL instruction
STACK This is how the CPU knows where to
resume when it returns from the called
CALL subroutine
Instruction And
Stack


The reason of incrementing SP after
8051
REGISTER
push is
BANKS AND Make sure that the stack is growing
STACK toward RAM location 7FH, from lower to
upper addresses
Incrementing Ensure that the stack will not reach the
Stack Pointer bottom of RAM and consequently run out

of stack space
If the stack pointer were decremented
after push
We would be using RAM locations 7, 6, 5, etc.
which belong to R7 to R0 of bank 0, the default
register bank


When 8051 is powered up, register
8051
REGISTER
bank 1 and the stack are using the
BANKS AND same memory space
STACK We can reallocate another section of RAM
to the stack
Stack and Bank
1 Conflict


Example 2-10
8051 Examining the stack, show the contents of the register and SP after
REGISTER execution of the following instructions. All value are in hex.
BANKS AND MOV SP, #5FH ;make RAM location 60H
STACK
;first stack location
MOV R2, #25H
MOV R1, #12H

Stack And Bank
MOV R4, #0F3H
PUSH 2
1 Conflict PUSH 1
(cont’) PUSH 4

Solution:
After PUSH 2 After PUSH 1 After PUSH 4
63 63 63 63
62 62 62 62 F3
61 61 61 12 61 12
60 60 25 60 25 60 25
Start SP = 5F SP = 60 SP = 61 SP = 62


JUMP, LOOP AND CALL
INSTRUCTIONS


Chung-Ping Young
楊中平


Repeating a sequence of instructions a
LOOP AND certain number of times is called a
JUMP loop
INSTRUCTIONS
Loop action is performed by
DJNZ reg, Label
Looping
The register is decremented
If it is not zero, it jumps to the target address
referred to by the label
A loop can be repeated a Prior to the start of loop the register is loaded
maximum of 255 times, if with the counter for the number of repetitions
R2 is FFH
Counter can be R0 – R7 or RAM location
;This program adds value 3 to the ACC ten times
MOV A,#0 ;A=0, clear ACC
MOV R2,#10 ;load counter R2=10
AGAIN: ADD A,#03 ;add 03 to ACC
DJNZ R2,AGAIN ;repeat until R2=0,10 times
MOV R5,A ;save A in R5


If we want to repeat an action more
LOOP AND
JUMP
times than 256, we use a loop inside a
INSTRUCTIONS loop, which is called nested loop
We use multiple registers to hold the
Nested Loop count

Write a program to (a) load the accumulator with the value 55H, and
(b) complement the ACC 700 times

MOV A,#55H ;A=55H
MOV R3,#10 ;R3=10, outer loop count
NEXT: MOV R2,#70 ;R2=70, inner loop count
AGAIN: CPL A ;complement A register
DJNZ R2,AGAIN ;repeat it 70 times
DJNZ R3,NEXT


Jump only if a certain condition is met
LOOP AND JZ label ;jump if A=0
JUMP MOV A,R0 ;A=R0
INSTRUCTIONS JZ OVER ;jump if A = 0
MOV A,R1 ;A=R1
JZ OVER ;jump if A = 0
Conditional ...
Jumps OVER: Can be used only for register A,
not any other register

Determine if R5 contains the value 0. If so, put 55H in it.
MOV A,R5 ;copy R5 to A
JNZ NEXT ;jump if A is not zero
MOV R5,#55H
NEXT: ...


(cont’)
LOOP AND JNC label ;jump if no carry, CY=0
JUMP If CY = 0, the CPU starts to fetch and execute
INSTRUCTIONS instruction from the address of the label
If CY = 1, it will not jump but will execute the next
Conditional instruction below JNC
Jumps Find the sum of the values 79H, F5H, E2H. Put the sum in registers
(cont’) R0 (low byte) and R5 (high byte).
MOV R5,#0
MOV A,#0 ;A=0
MOV R5,A ;clear R5
ADD A,#79H ;A=0+79H=79H
; JNC N_1 ;if CY=0, add next number
; INC R5 ;if CY=1, increment R5
N_1: ADD A,#0F5H ;A=79+F5=6E and CY=1
JNC N_2 ;jump if CY=0
INC R5 ;if CY=1,increment R5 (R5=1)
N_2: ADD A,#0E2H ;A=6E+E2=50 and CY=1
JNC OVER ;jump if CY=0
INC R5 ;if CY=1, increment 5
OVER: MOV R0,A ;now R0=50H, and R5=02

8051 conditional jump instructions
LOOP AND Instructions Actions
JUMP JZ Jump if A ＝ 0
INSTRUCTIONS JNZ Jump if A ≠ 0
DJNZ Decrement and Jump if A ≠ 0
Conditional CJNE A,byte Jump if A ≠ byte
Jump if byte ≠ #data
Jumps CJNE reg,#data
(cont’) JC Jump if CY ＝ 1
JNC Jump if CY ＝ 0
JB Jump if bit ＝ 1
JNB Jump if bit ＝ 0
JBC Jump if bit ＝ 1 and clear bit

All conditional jumps are short jumps
The address of the target must within
-128 to +127 bytes of the contents of PC


The unconditional jump is a jump in
LOOP AND which control is transferred
JUMP unconditionally to the target location
INSTRUCTIONS
LJMP (long jump)
Unconditional 3-byte instruction
Jumps First byte is the opcode
Second and third bytes represent the 16-bit
target address
– Any memory location from 0000 to FFFFH
SJMP (short jump)
2-byte instruction
First byte is the opcode
Second byte is the relative target address
– 00 to FFH (forward +127 and backward
-128 bytes from the current PC)


To calculate the target address of a
LOOP AND
JUMP
short jump (SJMP, JNC, JZ, DJNZ, etc.)
INSTRUCTIONS The second byte is added to the PC of the
instruction immediately below the jump
Calculating If the target address is more than -128
Short Jump to +127 bytes from the address below
Address
the short jump instruction

The assembler will generate an error
stating the jump is out of range


Line PC Opcode Mnemonic Operand
LOOP AND 01 0000 ORG 0000
JUMP 02 0000 7800 MOV R0,#0
03 0002 7455 MOV A,#55H
INSTRUCTIONS 04 0004 6003 JZ NEXT
05 0006 08 INC R0
Calculating 06 0007 04
+ AGAIN: INC A
07 0008 04 INC A
Short Jump 08 0009 2477 NEXT: ADD A,#77H
Address 09 000B 5005 JNC OVER
(cont’) 10 000D E4 CLR A
11 000E F8 MOV R0,A
12 000F F9
+ MOV R1,A
13 0010 FA MOV R2,A
14 0011 FB MOV R3,A
15 0012 2B OVER: ADD A,R3
16 0013 50F2 JNC AGAIN
17 0015 80FE + HERE: SJMP HERE
18 0017 END


Call instruction is used to call subroutine
CALL
Subroutines are often used to perform tasks
INSTRUCTIONS that need to be performed frequently
This makes a program more structured in
addition to saving memory space
LCALL (long call)
3-byte instruction
First byte is the opcode

Second and third bytes are used for address of
target subroutine
– Subroutine is located anywhere within 64K
byte address space
ACALL (absolute call)
2-byte instruction
11 bits are used for address within 2K-byte range


When a subroutine is called, control is
CALL
INSTRUCTIONS
transferred to that subroutine, the
processor
LCALL Saves on the stack the the address of the
instruction immediately below the LCALL
Begins to fetch instructions form the new
location
After finishing execution of the
subroutine
The instruction RET transfers control back
to the caller
Every subroutine needs RET as the last
instruction


ORG 0
BACK: MOV A,#55H ;load A with 55H
CALL MOV P1,A ;send 55H to port 1
INSTRUCTIONS LCALL
MOV
DELAY
A,#0AAH
;time
;load
delay
A with AA (in hex)
MOV P1,A ;send AAH to port 1
LCALL LCALL
SJMP
DELAY
BACK ;keep doing this indefinitely
(cont’) Upon executing “LCALL DELAY”,
the address of instruction below it,
The counter R5 is set to “MOV A,#0AAH” is pushed onto
FFH; so loop is repeated stack, and the 8051 starts to execute
255 times.
at 300H.
;---------- this is delay subroutine ------------
ORG 300H ;put DELAY at address 300H
DELAY: MOV R5,#0FFH ;R5=255 (FF in hex), counter
AGAIN: DJNZ R5,AGAIN ;stay here until R5 become 0
RET ;return to caller (when R5 =0)
END ;end of asm file
When R5 becomes 0, control falls to the
The amount of time delay depends RET which pops the address from the stack
on the frequency of the 8051 into the PC and resumes executing the
instructions after the CALL.

001 0000 ORG 0
002 0000 7455 BACK: MOV A,#55H ;load A with 55H
CALL 003 0002 F590 MOV P1,A ;send 55H to p1
INSTRUCTIONS 004
005
0004
0007
120300
74AA
LCALL DELAY
MOV A,#0AAH
;time
;load
delay
A with AAH
006 0009 F590 MOV P1,A ;send AAH to p1
CALL 007
008
000B
000E
120300
80F0
LCALL DELAY
SJMP BACK ;keep doing this
Instruction and 009 0010
Stack 010
011
0010
0300
;-------this is the delay subroutine------
ORG 300H
012 0300 DELAY:
013 0300 7DFF MOV R5,#0FFH ;R5=255
014 0302 DDFE AGAIN: DJNZ R5,AGAIN ;stay here
015 0304 22 RET ;return to caller
016 0305 END ;end of asm file

Stack frame after the first LCALL
0A
09 00 Low byte goes first
and high byte is last
08 07
SP = 09

01 0000 ORG 0
02 0000 7455 BACK: MOV A,#55H ;load A with 55H
03 0002 F590 MOV P1,A ;send 55H to p1
CALL 04 0004 7C99 MOV R4,#99H
05 0006 7D67 MOV R5,#67H
INSTRUCTIONS 06 0008 120300 LCALL DELAY ;time delay
07 000B 74AA MOV A,#0AAH ;load A with AA
08 000D F590 MOV P1,A ;send AAH to p1
Use PUSH/POP 09 000F 120300 LCALL DELAY
in Subroutine
10 0012 80EC SJMP BACK ;keeping doing
this
11 0014 ;-------this is the delay subroutine------
12 0300 ORG 300H
13 0300 C004 DELAY: PUSH 4 ;push R4
14 0302 C005 PUSH 5 ;push R5
Normally, the 15 0304 7CFF MOV R4,#0FFH;R4=FFH
number of PUSH 16 0306 7DFF NEXT: MOV R5,#0FFH;R5=FFH
and POP 17 0308 DDFE AGAIN: DJNZ R5,AGAIN
instructions must 18 030A DCFA DJNZ R4,NEXT
19 030C D005 POP 5 ;POP into R5
always match in any
20 030E D004 POP 4 ;POP into R4
called subroutine 21 0310 22 RET ;return to caller
22 0311 After first LCALL END PUSH 4
After After PUSH 5
;end of asm file
0B 0B 0B 67 R5
0A 0A 99 R4 0A 99 R4
09 00 PCH 09 00 PCH 09 00 PCH
08 0B PCL 08 0B PCL 08 0B PCL

;MAIN program calling subroutines
ORG 0
CALL MAIN: LCALL SUBR_1 It is common to have one
INSTRUCTIONS LCALL
LCALL
SUBR_2
SUBR_3
main program and many
subroutines that are called
from the main program
Calling
HERE: SJMP HERE
;-----------end of MAIN
Subroutines SUBR_1: ...
... This allows you to make
RET each subroutine into a
;-----------end of subroutine1 separate module
- Each module can be
SUBR_2: ...
... tested separately and then
RET brought together with
;-----------end of subroutine2 main program
- In a large program, the
SUBR_3: ... module can be assigned to
... different programmers
RET
;-----------end of subroutine3
END ;end of the asm file


The only difference between ACALL
CALL
and LCALL is
INSTRUCTIONS
The target address for LCALL can be
ACALL anywhere within the 64K byte address
The target address of ACALL must be
within a 2K-byte range
The use of ACALL instead of LCALL

can save a number of bytes of
program ROM space


ORG 0
CALL BACK: MOV
MOV
A,#55H
P1,A
;load
;send
A with
55H to
55H
port 1
INSTRUCTIONS LCALL DELAY ;time delay
MOV A,#0AAH ;load A with AA (in hex)
MOV P1,A ;send AAH to port 1
ACALL LCALL DELAY
(cont’) SJMP BACK ;keep doing this indefinitely
...

A rewritten program which is more efficiently
ORG 0
MOV A,#55H ;load A with 55H
BACK: MOV P1,A ;send 55H to port 1
ACALL DELAY ;time delay
CPL A ;complement reg A
SJMP BACK ;keep doing this indefinitely
...


CPU executing an instruction takes a
TIME DELAY
FOR VARIOUS
certain number of clock cycles
8051 CHIPS These are referred as to as machine cycles
The length of machine cycle depends
on the frequency of the crystal
oscillator connected to 8051
In original 8051, one machine cycle
lasts 12 oscillator periods
Find the period of the machine cycle for 11.0592 MHz crystal
frequency

Solution:
11.0592/12 = 921.6 kHz;
machine cycle is 1/921.6 kHz = 1.085μs


For 8051 system of 11.0592 MHz, find how long it takes to execute
TIME DELAY each instruction.
(a) MOV R3,#55 (b) DEC R3 (c) DJNZ R2 target
FOR VARIOUS (d) LJMP (e) SJMP (f) NOP (g) MUL AB
8051 CHIPS
(cont’) Solution:
Machine cycles Time to execute
(a) 1 1x1.085μs ＝ 1.085μs
(b) 1 1x1.085μs ＝ 1.085μs
(c) 2 2x1.085μs ＝ 2.17μs
(d) 2 2x1.085μs ＝ 2.17μs
(e) 2 2x1.085μs ＝ 2.17μs
(f) 1 1x1.085μs ＝ 1.085μs
(g) 4 4x1.085μs ＝ 4.34μs


Find the size of the delay in following program, if the crystal
TIME DELAY frequency is 11.0592MHz.
FOR VARIOUS
8051 CHIPS MOV A,#55H
AGAIN: MOV P1,A
ACALL DELAY
Delay CPL A
Calculation SJMP AGAIN A simple way to short jump
to itself in order to keep the
;---time delay-------
DELAY: MOV R3,#200 microcontroller busy
HERE: DJNZ R3,HERE HERE: SJMP HERE
RET We can use the following:
SJMP $
Solution:
Machine cycle
DELAY: MOV R3,#200 1
HERE: DJNZ R3,HERE 2
RET 2
Therefore, [(200x2)+1+2]x1.085μs ＝ 436.255μs.


FOR VARIOUS
8051 CHIPS Machine Cycle
DELAY: MOV R3,#250 1
HERE: NOP 1
Increasing NOP 1
Delay Using NOP 1
NOP 1
NOP DJNZ R3,HERE 2
RET 2

Solution:
The time delay inside HERE loop is
[250(1+1+1+1+2)]x1.085μs ＝ 1627.5μs.
Adding the two instructions outside loop we
have 1627.5μs + 3 x 1.085μs ＝ 1630.755μs


FOR VARIOUS Machine Cycle
8051 CHIPS DELAY: MOV R2,#200 1
Notice in nested loop,
AGAIN: MOV R3,#250 1
as in all other time
Large Delay HERE: NOP
NOP
1
1
delay loops, the time
Using Nested DJNZ R3,HERE 2
is approximate since
we have ignored the
Loop DJNZ R2,AGAIN 2
first and last
RET 2
instructions in the
subroutine.
Solution:
For HERE loop, we have (4x250)x1.085μs＝1085μs.
For AGAIN loop repeats HERE loop 200 times, so
we have 200x1085μs＝217000μs. But “MOV
R3,#250” and “DJNZ R2,AGAIN” at the start and
end of the AGAIN loop add (3x200x1.805)=651μs.
As a result we have 217000+651=217651μs.


Two factors can affect the accuracy of
TIME DELAY the delay
FOR VARIOUS
Crystal frequency
8051 CHIPS
The duration of the clock period of the machine
cycle is a function of this crystal frequency
Delay 8051 design
Calculation for The original machine cycle duration was set at
Other 8051 12 clocks

Advances in both IC technology and CPU
design in recent years have made the 1-clock
machine cycle a common feature
Clocks per machine cycle for various 8051 versions
Chip/Maker Clocks per Machine Cycle
AT89C51 Atmel 12
P89C54X2 Philips 6
DS5000 Dallas Semi 4
DS89C420/30/40/50 Dallas Semi 1

Find the period of the machine cycle (MC) for various versions of
TIME DELAY 8051, if XTAL=11.0592 MHz.
(a) AT89C51 (b) P89C54X2 (c) DS5000 (d) DS89C4x0
FOR VARIOUS
8051 CHIPS Solution:
(a) 11.0592MHz/12 = 921.6kHz;
MC is 1/921.6kHz = 1.085μs ＝ 1085ns
Delay (b) 11.0592MHz/6 = 1.8432MHz;
MC is 1/1.8432MHz = 0.5425μs ＝ 542ns
Calculation for (c) 11.0592MHz/4 = 2.7648MHz ;
Other 8051 MC is 1/2.7648MHz = 0.36μs ＝ 360ns
(cont’) (d) 11.0592MHz/1 = 11.0592MHz;
MC is 1/11.0592MHz = 0.0904μs ＝ 90ns


Instruction 8051 DSC89C4x0
MOV R3,#55 1 2
TIME DELAY DEC R3 1 1
FOR VARIOUS DJNZ R2 target 2 4
LJMP 2 3
8051 CHIPS SJMP 2 3
NOP 1 1
Delay MUL AB 4 9
Calculation for For an AT8051 and DSC89C4x0 system of 11.0592 MHz, find how
Other 8051 long it takes to execute each instruction.
(a) MOV R3,#55 (b) DEC R3 (c) DJNZ R2 target
(cont’)

(d) LJMP (e) SJMP (f) NOP (g) MUL AB

Solution:
AT8051 DS89C4x0
(a) 1 1085ns ＝ 1085ns 2 90ns = 180ns
(b) 1 1085ns ＝ 1085ns 1 90ns = 90ns
(c) 2 1085ns ＝ 2170ns 4 90ns = 360ns
(d) 2 1085ns ＝ 2170ns 3 90ns = 270ns
(e) 2 1085ns ＝ 2170ns 3 90ns = 270ns
(f) 1 1085ns ＝ 1085ns 1 90ns = 90ns
(g) 4 1085ns ＝ 4340ns 9 90ns = 810ns

I/O PORT
PROGRAMMING


Chung-Ping Young
楊中平


Provides
+5V supply
I/O voltage to
PROGRAMMING 8051 Pin Diagram the chip
P1.0 1 40 Vcc
A total of 32 P1.1 2 39 P0.0 (AD0)
pins are set P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
aside for the P1 P1.4 5 36 P0.3 (AD3)
four ports P0, P1.5 6 35 P0.4 (AD4) P0
P1.6 7 34 P0.5 (AD5)
P1, P2, P3, P1.7 8 8051 33 P0.6 (AD6)
where each RST 9 32 P0.7 (AD7)
port takes 8 (RXD) P3.0 10
(8031) 31 -EA/VPP
(TXD) P3.1 30 ALE/PROG
pins (-INT0) P3.2
11
12
(89420) 29 -PSEN
(-INT1) P3.3 13 28 P2.7 (A15)
P3 (T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 26 P2.5 (A13)
(-WR) P3.6 16 25 P2.4 (A12)
(-RD )P3.7 17 24 P2.3 (A11) P2
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
Grond


The four 8-bit I/O ports P0, P1, P2 and
I/O
PROGRAMMING
P3 each uses 8 pins
All the ports upon RESET are
I/O Port Pins configured as input, ready to be used
as input ports
When the first 0 is written to a port, it

becomes an output
P1.0
P1.1
1
2
40
39
Vcc
P0.0(AD0)
To reconfigure it as an input, a 1 must be
sent to the port
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6
P1.7
7
8
34
33
32
P0.5(AD5)
P0.6(AD6) To use any of these ports as an input port, it
RST 9 P0.7(AD7)
(RXD)P3.0
(TXD)P3.1
10
8051 31
11(8031)30
-EA/VPP
ALE/PROG must be programmed
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


It can be used for input or output,
I/O
PROGRAMMING
each pin must be connected externally
to a 10K ohm pull-up resistor
Port 0 This is due to the fact that P0 is an open
drain, unlike P1, P2, and P3
Open drain is a term used for MOS chips in the
same way that open collector is used for TTL
chips
Vcc
P1.0
P1.1
1
2
40
39
Vcc
P0.0(AD0) 10 K
P1.2
P1.3
3
4
38
37
P0.1(AD1)
P0.2(AD2) P0.X
P1.4 5 36 P0.3(AD3) P0.0
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5) P0.1
33 P0.6(AD6)

Port 0
P1.7 8 P0.2
RST 9 32
8051 31 P0.7(AD7) 8051
(RXD)P3.0 10 -EA/VPP P0.3
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN P0.4
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14) P0.5
(T1)P3.5 15 26 P2.5(A13) P0.6
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11) P0.7
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


The following code will continuously send out to port 0 the
I/O alternating value 55H and AAH
PROGRAMMING BACK: MOV A,#55H
MOV P0,A
Port 0 ACALL DELAY
(cont’) MOV A,#0AAH
MOV P0,A
ACALL DELAY

SJMP BACK

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


In order to make port 0 an input, the
I/O port must be programmed by writing 1
PROGRAMMING
to all the bits
Port 0 as Input Port 0 is configured first as an input port by writing 1s to it, and then
data is received from that port and sent to P1
MOV A,#0FFH ;A=FF hex
MOV P0,A ;make P0 an i/p port
;by writing it all 1s
BACK: MOV A,P0 ;get data from P0
P1.0 1 40 Vcc
P1.1
P1.2
2
3
39
38
P0.0(AD0)
P0.1(AD1)
MOV P1,A ;send it to port 1
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3) SJMP BACK ;keep doing it
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


Port 0 is also designated as AD0-AD7,
I/O
PROGRAMMING
allowing it to be used for both address
and data
Dual Role of When connecting an 8051/31 to an
Port 0 external memory, port 0 provides both
address and data

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


Port 1 can be used as input or output
I/O
PROGRAMMING In contrast to port 0, this port does not
need any pull-up resistors since it already
Port 1 has pull-up resistors internally
Upon reset, port 1 is configured as an
input port
The following code will continuously send out to port 0 the
alternating value 55H and AAH
P1.0 1 40 Vcc
P1.1
P1.2
2
3
39
38
P0.0(AD0)
P0.1(AD1)
MOV A,#55H
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3) BACK: MOV P1,A
P1.5 6 35 P0.4(AD4)
P1.6
P1.7
7
8
34
33
P0.5(AD5)
P0.6(AD6)
ACALL DELAY
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP CPL A
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2
(INT1)P3.3
12
13
29
28
-PSEN
P2.7(A15)
SJMP BACK
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


To make port 1 an input port, it must
I/O
PROGRAMMING
be programmed as such by writing 1
to all its bits
Port 1 as Input Port 1 is configured first as an input port by writing 1s to it, then data
is received from that port and saved in R7 and R5
MOV A,#0FFH ;A=FF hex

MOV P1,A ;make P1 an input port
;by writing it all 1s
MOV A,P1 ;get data from P1
P1.0 1 40 Vcc
P1.1 2
3
39
38
P0.0(AD0)
P0.1(AD1)
MOV R7,A ;save it to in reg R7
P1.2
4 37 P0.2(AD2)
P1.3
P1.4 5 36 P0.3(AD3) ACALL DELAY ;wait
P1.5 6 35 P0.4(AD4)
P1.6
P1.7
7
8
34
33
P0.5(AD5)
P0.6(AD6)
MOV A,P1 ;another data from P1
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP MOV R5,A ;save it to in reg R5
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


I/O
PROGRAMMING Just like P1, port 2 does not need any pull-
up resistors since it already has pull-up
Port 2 resistors internally
Upon reset, port 2 is configured as an input
port

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


To make port 2 an input port, it must
I/O
PROGRAMMING
be programmed as such by writing 1 to
all its bits
Port 2 as Input In many 8051-based system, P2 is used
or Dual Role as simple I/O
In 8031-based systems, port 2 must be

used along with P0 to provide the 16-
P1.0
P1.1
P1.2
1
2
3
40
39
38
Vcc
P0.0(AD0)
P0.1(AD1)
bit address for the external memory
P1.3 4 37 P0.2(AD2)
P1.4
P1.5
P1.6
5
6
7
36
35
34
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
Port 2 is also designated as A8 – A15,
indicating its dual function
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG

Port 0 provides the lower 8 bits via A0 – A7
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


I/O
PROGRAMMING Port 3 does not need any pull-up resistors
Port 3 is configured as an input port upon
Port 3 reset, this is not the way it is most
commonly used

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


Port 3 has the additional function of
I/O
PROGRAMMING
providing some extremely important
signals
Port 3 P3 Bit Function Pin
Serial
(cont’) P3.0 RxD 10 communications
P3.1 TxD 11
External

P3.2 INT0 12 interrupts
P3.3 INT1 13
P1.0 1
2
40
39
Vcc
P0.0(AD0) P3.4 T0 14 Timers
P1.1
P1.2 3 38 P0.1(AD1)
37
P3.5 T1 15
P1.3 4 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5) Read/Write signals
P1.7
RST
8
9
33
32
8051 31
P0.6(AD6)
P0.7(AD7) P3.6 WR 16 of external memories
(RXD)P3.0 10 -EA/VPP
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
11(8031)30
12 29
28
ALE/PROG
-PSEN
P2.7(A15)
P3.7 RD 17
13
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5
(WR)P3.6
15
16
26
25
P2.5(A13)
P2.4(A12) In systems based on 8751, 89C51 or
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10) DS89C4x0, pins 3.6 and 3.7 are used for I/O
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) while the rest of the pins in port 3 are
normally used in the alternate function role

Write a program for the DS89C420 to toggle all the bits of P0, P1,
and P2 every 1/4 of a second
I/O ORG 0
PROGRAMMING BACK: MOV A,#55H
MOV P0,A
MOV P1,A
Port 3 MOV P2,A
ACALL QSDELAY ;Quarter of a second
(cont’) MOV A,#0AAH
MOV P0,A
MOV P1,A
MOV P2,A
ACALL QSDELAY
P1.0 1 40 Vcc SJMP BACK
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1) QSDELAY: Delay
P1.3 4 37 P0.2(AD2)
P1.4
P1.5
5
6
36
35
P0.3(AD3)
P0.4(AD4)
MOV R5,#11 = 11 × 248 × 255 × 4 MC × 90 ns
P1.6
P1.7
7
8
34
33
P0.5(AD5)
P0.6(AD6)
H3: MOV R4,#248 = 250,430 µs
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP H2: MOV R3,#255
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2
(INT1)P3.3
12 29
28
-PSEN
P2.7(A15)
H1: DJNZ R3,H1 ;4 MC for DS89C4x0
13
(T0)P3.4
(T1)P3.5
14
15
27
26
P2.6(A14)
P2.5(A13)
DJNZ R4,H2
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11) DJNZ R5,H3
XTAL2 18 23 P2.2(A10)
XTAL1
GND
19
20
22
21
P2.1(A9)
P2.0(A8)
RET
END

The entire 8 bits of Port 1 are accessed
BACK: MOV A,#55H
I/O MOV P1,A
PROGRAMMING ACALL
MOV
DELAY
A,#0AAH
MOV P1,A
Different ways ACALL
SJMP
DELAY
BACK
of Accessing
Entire 8 Bits Rewrite the code in a more efficient manner by accessing the port
directly without going through the accumulator
BACK: MOV P1,#55H
ACALL DELAY
MOV P1,#0AAH
ACALL DELAY
SJMP BACK

Another way of doing the same thing
MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK

Sometimes we need to access only 1
I/O BIT
MANIPULATION
or 2 bits of the port
PROGRAMMING BACK: CPL
ACALL
P1.2
DELAY
;complement P1.2

SJMP BACK
I/O Ports
and Bit ;another variation of the above program
AGAIN: SETB P1.2 ;set only P1.2
Addressability ACALL DELAY
CLR P1.2 ;clear only P1.2
ACALL DELAY
SJMP AGAIN P0 P1 P2 P3 Port Bit
P0.0 P1.0 P2.0 P3.0 D0
P0.1 P1.1 P2.1 P3.1 D1
P0.2 P1.2 P2.2 P3.2 D2
P0.3 P1.3 P2.3 P3.3 D3
P0.4 P1.4 P2.4 P3.4 D4
P0.5 P1.5 P2.5 P3.5 D5
P0.6 P1.6 P2.6 P3.6 D6
P0.7 P1.7 P2.7 P3.7 D7


Example 4-2
Write the following programs.
I/O BIT Create a square wave of 50% duty cycle on bit 0 of port 1.
MANIPULATION Solution:
PROGRAMMING The 50% duty cycle means that the “on” and “off” state (or the high
and low portion of the pulse) have the same length. Therefore,
I/O Ports we toggle P1.0 with a time delay in between each state.
and Bit HERE: SETB P1.0 ;set to high bit 0 of port 1
LCALL DELAY ;call the delay subroutine
Addressability CLR P1.0 ;P1.0=0
(cont’) LCALL DELAY
SJMP HERE ;keep doing it
Another way to write the above program is:
HERE: CPL P1.0 ;set to high bit 0 of port 1
LCALL DELAY ;call the delay subroutine
SJMP HERE ;keep doing it
8051

P1.0


Instructions that are used for signal-bit
I/O BIT
operations are as following
MANIPULATION
PROGRAMMING Single-Bit Instructions
Instruction Function
I/O Ports SETB bit Set the bit (bit = 1)
and Bit CLR bit Clear the bit (bit = 0)
Addressability CPL bit Complement the bit (bit = NOT bit)
(cont’) JB bit, target Jump to target if bit = 1 (jump if bit)
JNB bit, target Jump to target if bit = 0 (jump if no bit)
JBC bit, target Jump to target if bit = 1, clear bit
(jump if bit, then clear)


The JNB and JB instructions are widely
I/O BIT used single-bit operations
MANIPULATION They allow you to monitor a bit and make
PROGRAMMING a decision depending on whether it’s 0 or 1
These two instructions can be used for any
Checking an bits of I/O ports 0, 1, 2, and 3
Input Bit Port 3 is typically not used for any I/O, either

single-bit or byte-wise

Instructions for Reading an Input Port

Mnemonic Examples Description
MOV A,PX MOV A,P2 Bring into A the data at P2 pins
JNB PX.Y, .. JNB P2.1,TARGET Jump if pin P2.1 is low
JB PX.Y, .. JB P1.3,TARGET Jump if pin P1.3 is high
MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY


Example 4-3
I/O BIT
Write a program to perform the following:
MANIPULATION (a) Keep monitoring the P1.2 bit until it becomes high
PROGRAMMING (b) When P1.2 becomes high, write value 45H to port 0
(c) Send a high-to-low (H-to-L) pulse to P2.3
Solution:
Checking an SETB P1.2 ;make P1.2 an input
Input Bit MOV A,#45H ;A=45H
(cont’) AGAIN: JNB P1.2,AGAIN ; get out when P1.2=1
MOV P0,A ;issue A to P0
SETB P2.3 ;make P2.3 high
CLR P2.3 ;make P2.3 low for H-to-L


Example 4-4
I/O BIT
Assume that bit P2.3 is an input and represents the condition of an
MANIPULATION oven. If it goes high, it means that the oven is hot. Monitor the bit
PROGRAMMING continuously. Whenever it goes high, send a high-to-low pulse to port
P1.5 to turn on a buzzer.
Solution:
Checking an
HERE: JNB P2.3,HERE ;keep monitoring for high
Input Bit SETB P1.5 ;set bit P1.5=1
(cont’) CLR P1.5 ;make high-to-low
SJMP HERE ;keep repeating


Example 4-5
I/O BIT
A switch is connected to pin P1.7. Write a program to check the status
MANIPULATION of SW and perform the following:
PROGRAMMING (a) If SW=0, send letter ‘N’ to P2
(b) If SW=1, send letter ‘Y’ to P2

Checking an Solution:
Input Bit
SETB P1.7 ;make P1.7 an input
AGAIN: JB P1.2,OVER ;jump if P1.7=1
(cont’)
MOV P2,#’N’ ;SW=0, issue ‘N’ to P2
SJMP AGAIN ;keep monitoring
OVER: MOV P2,#’Y’ ;SW=1, issue ‘Y’ to P2


Example 4-6
I/O BIT
MANIPULATION of SW and perform the following:
PROGRAMMING (a) If SW=0, send letter ‘N’ to P2
(b) If SW=1, send letter ‘Y’ to P2
Use the carry flag to check the switch status.
Reading Single Solution:
Bit into Carry SETB P1.7 ;make P1.7 an input
Flag AGAIN: MOV C,P1.2 ;read SW status into CF
JC OVER ;jump if SW=1
MOV P2,#’N’ ;SW=0, issue ‘N’ to P2
OVER: MOV P2,#’Y’ ;SW=1, issue ‘Y’ to P2


Example 4-7
I/O BIT
A switch is connected to pin P1.0 and an LED to pin P2.7. Write a
MANIPULATION program to get the status of the switch and send it to the LED
PROGRAMMING
Solution:
SETB P1.7 ;make P1.7 an input
Reading Single AGAIN: MOV C,P1.0 ;read SW status into CF
Bit into Carry MOV P2.7,C ;send SW status to LED

Flag SJMP AGAIN ;keep repeating
(cont’)

The instruction
‘MOV
P2.7,P1.0’ is
wrong , since such
However ‘MOV an instruction does
P2,P1’ is a valid not exist
instruction


In reading a port
I/O BIT Some instructions read the status of port
MANIPULATION pins
PROGRAMMING Others read the status of an internal port
latch
Reading Input Therefore, when reading ports there
Pins vs. Port are two possibilities:
Latch Read the status of the input pin
Read the internal latch of the output port
Confusion between them is a major
source of errors in 8051 programming
Especially where external hardware is
concerned


Some instructions read the contents of
READING
INPUT PINS VS.
an internal port latch instead of
PORT LATCH reading the status of an external pin
For example, look at the ANL P1,A
Reading Latch instruction and the sequence of actions is
for Output Port executed as follow
1. It reads the internal latch of the port and
brings that data into the CPU
2. This data is ANDed with the contents of
register A
3. The result is rewritten back to the port latch
4. The port pin data is changed and now has the
same value as port latch


Read-Modify-Write
READING
The instructions read the port latch
INPUT PINS VS.
normally read a value, perform an
PORT LATCH operation then rewrite it back to the port
latch
Reading Latch Instructions Reading a latch (Read-Modify-Write)
for Output Port Mnemonics Example
(cont’) ANL PX ANL P1,A
ORL PX ORL P2,A
XRL PX XRL P0,A
JBC PX.Y,TARGET JBC P1.1,TARGET
CPL PX.Y CPL P1.2
INC PX INC P1
DEC PX DEC P2
DJNZ PX.Y,TARGET DJNZ P1,TARGET
MOV PX.Y,C MOV P1.2,C
CLR PX.Y CLR P2.3 Note: x is 0, 1, 2,
SETB PX.Y SETB P2.3 or 3 for P0 – P3


The ports in 8051 can be accessed by
I/O BIT
MANIPULATION the Read-modify-write technique
PROGRAMMING This feature saves many lines of code by
combining in a single instruction all three
Read-modify- actions
write Feature 1. Reading the port

2. Modifying it
3. Writing to the port
MOV P1,#55H ;P1=01010101
AGAIN: XRL P1,#0FFH ;EX-OR P1 with 1111 1111
ACALL DELAY
SJMP BACK


ADDRESSING MODES


Chung-Ping Young
楊中平


The CPU can access data in various
ADDRESSING
MODES
ways, which are called addressing
modes
Immediate
Register
Direct Accessing
memories
Register indirect

Indexed


The source operand is a constant
IMMEDIATE
ADDRESSING The immediate data must be preceded by
MODE the pound sign, “#”
Can load information into any registers,
including 16-bit DPTR register
DPTR can also be accessed as two 8-bit
registers, the high byte DPH and low byte DPL

MOV A,#25H ;load 25H into A
MOV R4,#62 ;load 62 into R4
MOV B,#40H ;load 40H into B
MOV DPTR,#4521H ;DPTR=4512H
MOV DPL,#21H ;This is the same
MOV DPH,#45H ;as above
;illegal!! Value > 65535 (FFFFH)
MOV DPTR,#68975


We can use EQU directive to access
IMMEDIATE
ADDRESSING
immediate data
MODE Count EQU 30
... ...
(cont’) MOV R4,#COUNT ;R4=1EH
MOV DPTR,#MYDATA ;DPTR=200H

ORG 200H
MYDATA: DB “America”

We can also use immediate addressing
mode to send data to 8051 ports
MOV P1,#55H


Use registers to hold the data to be
REGISTER manipulated
ADDRESSING MOV A,R0 ;copy contents of R0 into A
MODE
ADD A,R5 ;add contents of R5 to A
ADD A,R7 ;add contents of R7 to A
MOV R6,A ;save accumulator in R6

The source and destination registers
must match in size

MOV DPTR,A will give an error
MOV DPTR,#25F5H
MOV R7,DPL
MOV R6,DPH

The movement of data between Rn
registers is not allowed
MOV R4,R7 is invalid

It is most often used the direct
ACCESSING
MEMORY
addressing mode to access RAM
locations 30 – 7FH
Direct The entire 128 bytes of RAM can be
Addressing accessed Direct addressing mode
Mode The register bank locations are accessed
by the register names

MOV A,4 ;is same as
MOV A,R4 ;which means copy R4 into A

Contrast this with immediate
addressing mode Register addressing mode

There is no “#” sign in the operand
MOV R0,40H ;save content of 40H in R0
MOV 56H,A ;save content of A in 56H

The SFR (Special Function Register)
ACCESSING
MEMORY
can be accessed by their names or by
their addresses
SFR Registers MOV 0E0H,#55H ;is the same as
and Their MOV A,#55h ;load 55H into A
Addresses MOV 0F0H,R0 ;is the same as
MOV B,R0 ;copy R0 into B

The SFR registers have addresses
between 80H and FFH
Not all the address space of 80 to FF is
used by SFR
The unused locations 80H to FFH are
reserved and must not be used by the
8051 programmer

Special Function Register (SFR) Addresses
Symbol Name Address
ACCESSING ACC* Accumulator 0E0H
MEMORY B* B register 0F0H
PSW* Program status word 0D0H
SFR Registers SP Stack pointer 81H

and Their DPTR Data pointer 2 bytes

Addresses DPL Low byte 82H

(cont’) DPH High byte 83H

P0* Port 0 80H
P1* Port 1 90H
P2* Port 2 0A0H
P3* Port 3 0B0H
IP* Interrupt priority control 0B8H
IE* Interrupt enable control 0A8H
… … …


Special Function Register (SFR) Addresses
Symbol Name Address
ACCESSING TMOD Timer/counter mode control 89H
MEMORY TCON* Timer/counter control 88H

T2CON* Timer/counter 2 control 0C8H
SFR Registers T2MOD Timer/counter mode control OC9H
and Their TH0 Timer/counter 0 high byte 8CH
Addresses TL0 Timer/counter 0 low byte 8AH
(cont’) TH1 Timer/counter 1 high byte 8DH
TL1 Timer/counter 1 low byte 8BH
TH2 Timer/counter 2 high byte 0CDH
TL2 Timer/counter 2 low byte 0CCH
RCAP2H T/C 2 capture register high byte 0CBH
RCAP2L T/C 2 capture register low byte 0CAH
SCON* Serial control 98H
SBUF Serial data buffer 99H
PCON Power ontrol 87H

* Bit addressable

Example 5-1
ACCESSING
MEMORY Write code to send 55H to ports P1 and P2, using
(a) their names (b) their addresses

SFR Registers Solution :
(a) MOV A,#55H ;A=55H
and Their
MOV P1,A ;P1=55H
Addresses MOV P2,A ;P2=55H
(cont’)
(b) From Table 5-1, P1 address=80H; P2 address=A0H

MOV A,#55H ;A=55H
MOV 80H,A ;P1=55H
MOV 0A0H,A ;P2=55H


Only direct addressing mode is allowed
ACCESSING
MEMORY
for pushing or popping the stack
PUSH A is invalid
Stack and Pushing the accumulator onto the stack
Direct must be coded as PUSH 0E0H
Addressing Example 5-2
Mode Show the code to push R5 and A onto the stack and then pop them

back them into R2 and B, where B = A and R2 = R5

Solution:
PUSH 05 ;push R5 onto stack
PUSH 0E0H ;push register A onto stack
POP 0F0H ;pop top of stack into B
;now register B = register A
POP 02 ;pop top of stack into R2
;now R2=R6


A register is used as a pointer to the
ACCESSING
MEMORY
data
Only register R0 and R1 are used for this
Register purpose
Indirect R2 – R7 cannot be used to hold the
Addressing address of an operand located in RAM
Mode When R0 and R1 hold the addresses of

RAM locations, they must be preceded
by the “@” sign
MOV A,@R0 ;move contents of RAM whose
;address is held by R0 into A
MOV @R1,B ;move contents of B into RAM
;whose address is held by R1


Example 5-3
Write a program to copy the value 55H into RAM memory locations
ACCESSING 40H to 41H using
MEMORY (a) direct addressing mode, (b) register indirect addressing mode
without a loop, and (c) with a loop

Register Solution:
(a)
Indirect MOV A,#55H ;load A with value 55H
MOV 40H,A ;copy A to RAM location 40H
Addressing MOV 41H.A ;copy A to RAM location 41H
Mode (b)
MOV A,#55H ;load A with value 55H
(cont’) MOV R0,#40H ;load the pointer. R0=40H
MOV @R0,A ;copy A to RAM R0 points to
INC R0 ;increment pointer. Now R0=41h
MOV @R0,A ;copy A to RAM R0 points to
(c)
MOV A,#55H ;A=55H
MOV R0,#40H ;load pointer.R0=40H,
MOV R2,#02 ;load counter, R2=3
AGAIN: MOV @R0,A ;copy 55 to RAM R0 points to
INC R0 ;increment R0 pointer
DJNZ R2,AGAIN ;loop until counter = zero


The advantage is that it makes
ACCESSING
MEMORY
accessing data dynamic rather than
static as in direct addressing mode
Register Looping is not possible in direct
Indirect addressing mode
Addressing Example 5-4
Mode Write a program to clear 16 RAM locations starting at RAM address

(cont’) 60H
Solution:
CLR A ;A=0
MOV R1,#60H ;load pointer. R1=60H
MOV R7,#16 ;load counter, R7=16
AGAIN: MOV @R1,A ;clear RAM R1 points to
INC R1 ;increment R1 pointer
DJNZ R7,AGAIN ;loop until counter=zero


Example 5-5
ACCESSING
MEMORY Write a program to copy a block of 10 bytes of data from 35H to 60H
Solution:
Register MOV R0,#35H ;source pointer
Indirect MOV R1,#60H ;destination pointer
MOV R3,#10 ;counter
Addressing BACK: MOV A,@R0 ;get a byte from source
Mode MOV @R1,A ;copy it to destination
(cont’) INC R0 ;increment source pointer
INC R1 ;increment destination pointer
DJNZ R3,BACK ;keep doing for ten bytes


R0 and R1 are the only registers that
ACCESSING
MEMORY
can be used for pointers in register
indirect addressing mode
Register Since R0 and R1 are 8 bits wide, their
Indirect use is limited to access any
Addressing
information in the internal RAM
Mode
Whether accessing externally

(cont’)
connected RAM or on-chip ROM, we
need 16-bit pointer
In such case, the DPTR register is used


Indexed addressing mode is widely
ACCESSING
MEMORY
used in accessing data elements of
look-up table entries located in the
Indexed program ROM
Addressing The instruction used for this purpose is
Mode and MOVC A,@A+DPTR
On-chip ROM
Use instruction MOVC, “C” means code

Access
The contents of A are added to the 16-bit
register DPTR to form the 16-bit address
of the needed data


Example 5-6

ACCESSING In this program, assume that the word “USA” is burned into ROM
locations starting at 200H. And that the program is burned into ROM
MEMORY locations starting at 0. Analyze how the program works and state
where “USA” is stored after this program is run.
Indexed Solution:
Addressing
ORG
0000H ;burn into ROM starting at 0
DPTR=200H, A=0 MOV
DPTR,#200H ;DPTR=200H look-up table addr
Mode and On-
DPTR=200H, A=55H
CLR
A
MOVC
;clear A(A=0)
A,@A+DPTR ;get the char from code space
chip ROMA=55H
DPTR=201H,
MOV
R0,A
INC
DPTR
;save it in R0
;DPTR=201 point to next char

Access CLR
A ;clear A(A=0)
MOVC A,@A+DPTR ;get the next char R0=55H
(cont’)
DPTR=201H, A=0
MOV R1,A ;save it in R1
DPTR=201H, A=53H INC DPTR ;DPTR=202 point to next char
CLR A ;clear A(A=0)
DPTR=202H, A=53H MOVC A,@A+DPTR ;get the next char R1=53H
MOV R2,A ;save it in R2
Here: SJMP HERE ;stay here
;Data is burned into code space starting at 200H
202 A
201 S ORG 200H R2=41H
MYDATA:DB “USA”
200 U END ;end of program

The look-up table allows access to
ACCESSING
elements of a frequently used table
MEMORY
with minimum operations
Look-up Table Example 5-8
Write a program to get the x value from P1 and send x2 to P2,
(cont’)
continuously
Solution:
ORG 0

MOV DPTR,#300H ;LOAD TABLE ADDRESS
MOV A,#0FFH ;A=FF
MOV P1,A ;CONFIGURE P1 INPUT PORT
BACK:MOV A,P1 ;GET X
MOV A,@A+DPTR ;GET X SQAURE FROM TABLE
MOV P2,A ;ISSUE IT TO P2
SJMP BACK ;KEEP DOING IT
ORG 300H
XSQR_TABLE:
DB 0,1,4,9,16,25,36,49,64,81
END


In many applications, the size of
ACCESSING program code does not leave any
MEMORY room to share the 64K-byte code
space with data
Indexed
The 8051 has another 64K bytes of
Addressing
memory space set aside exclusively for
Mode and data storage
MOVX This data memory space is referred to as

external memory and it is accessed only by the
MOVX instruction
The 8051 has a total of 128K bytes of
memory space
64K bytes of code and 64K bytes of data
The data space cannot be shared between
code and data

In many applications we use RAM
ACCESSING
MEMORY
locations 30 – 7FH as scratch pad
We use R0 – R7 of bank 0
RAM Locations Leave addresses 8 – 1FH for stack usage
30 – 7FH as If we need more registers, we simply use
Scratch Pad RAM locations 30 – 7FH
Example 5-10

Write a program to toggle P1 a total of 200 times. Use RAM
location 32H to hold your counter value instead of registers R0 –
R7
Solution:
MOV P1,#55H ;P1=55H
MOV 32H,#200 ;load counter value
;into RAM loc 32H
LOP1: CPL P1 ;toggle P1
ACALL DELAY
DJNZ 32H,LOP1 ;repeat 200 times

Many microprocessors allow program
BIT to access registers and I/O ports in
ADDRESSES byte size only
However, in many applications we need to
check a single bit
One unique and powerful feature of
the 8051 is single-bit operation
Single-bit instructions allow the

programmer to set, clear, move, and
complement individual bits of a port,
memory, or register
It is registers, RAM, and I/O ports that
need to be bit-addressable
ROM, holding program code for execution, is
not bit-addressable


The bit-addressable RAM location are
BIT 20H to 2FH
ADDRESSES These 16 bytes provide 128 bits of RAM
bit-addressability, since 16 × 8 = 128
Bit- 0 to 127 (in decimal) or 00 to 7FH
Addressable The first byte of internal RAM location 20H
RAM has bit address 0 to 7H
The last byte of 2FH has bit address 78H
to 7FH

Internal RAM locations 20-2FH are
both byte-addressable and bit-
addressable
Bit address 00-7FH belong to RAM byte
addresses 20-2FH
Bit address 80-F7H belong to SFR P0,
P1, …


7F

General purpose RAM
30

BIT 2F
2E
7F
77
7E
76
7D
75
7C
74
7B
73
7A
72
79
71
78
70
ADDRESSES 2D 6F 6E 6D 6C 6B 6A 69 68
2C 67 66 65 64 63 62 61 60

Bit-addressable 2B 5F 5E 5D 5C 5B 5A 59 58
Bit- locations 2A 57 56 55 54 53 52 51 50

Addressable 29
28
4F
47
4E
46
4D
45
4C
44
4B
43
4A
42
49
41
48
40
RAM 27 3F 3E 3D 3C 3B 3A 39 38

(cont’) Byte address 26 37 36 35 34 33 32 31 30
25 2F 2E 2D 2C 2B 2A 29 28
24 27 26 25 24 23 22 21 20
23 1F 1E 1D 1C 1B 1A 19 18
22 17 16 15 14 13 12 11 10
21 0F 0E 0D 0C 0B 0A 09 08
20 07 06 05 04 03 02 01 00
1F
18
Bank 3
17
10
Bank 2
0F
08
Bank 1
07
00
Default register bank for R0-R7


Example 5-11
BIT Find out to which by each of the following bits belongs. Give the
ADDRESSES address of the RAM byte in hex
(a) SETB 42H, (b) CLR 67H, (c) CLR 0FH
(d) SETB 28H, (e) CLR 12, (f) SETB 05
Bit- Solution:
D7 D6 D5 D4 D3 D2 D1 D0
2F 7F 7E 7D 7C 7B 7A 79 78
Addressable 2E 77 76 75 74 73 72 71 70

RAM (a) D2 of RAM location 28H 2D 6F 6E 6D 6C 6B 6A 69 68
2C 67 66 65 64 63 62 61 60
(cont’) (b) D7 of RAM location 2CH 2B 5F 5E 5D 5C 5B 5A 59 58
2A 57 56 55 54 53 52 51 50

(c) D7 of RAM location 21H 29 4F 4E 4D 4C 4B 4A 49 48
28 47 46 45 44 43 42 41 40
27 3F 3E 3D 3C 3B 3A 39 38
(d) D0 of RAM location 25H
26 37 36 35 34 33 32 31 30
25 2F 2E 2D 2C 2B 2A 29 28
(e) D4 of RAM location 21H
24 27 26 25 24 23 22 21 20
23 1F 1E 1D 1C 1B 1A 19 18
(f) D5 of RAM location 20H 22 17 16 15 14 13 12 11 10
21 0F 0E 0D 0C 0B 0A 09 08
20 07 06 05 04 03 02 01 00


To avoid confusion regarding the
BIT
ADDRESSES
addresses 00 – 7FH
The 128 bytes of RAM have the byte
Bit- addresses of 00 – 7FH can be accessed in
Addressable byte size using various addressing modes
RAM Direct and register-indirect
(cont’) The 16 bytes of RAM locations 20 – 2FH

have bit address of 00 – 7FH
We can use only the single-bit instructions and
these instructions use only direct addressing
mode


Instructions that are used for signal-bit
BIT
ADDRESSES
operations are as following
Single-Bit Instructions
Bit- Instruction Function
Addressable SETB bit Set the bit (bit = 1)
RAM CLR bit Clear the bit (bit = 0)
(cont’)
CPL bit Complement the bit (bit = NOT bit)
JB bit, target Jump to target if bit = 1 (jump if bit)
JNB bit, target Jump to target if bit = 0 (jump if no bit)
JBC bit, target Jump to target if bit = 1, clear bit
(jump if bit, then clear)


While all of the SFR registers are byte-
BIT addressable, some of them are also bit-
ADDRESSES addressable
The P0 – P3 are bit addressable
I/O Port
Bit Addresses We can access either the entire 8 bits
or any single bit of I/O ports P0, P1, P2,
and P3 without altering the rest
When accessing a port in a single-bit

manner, we use the syntax SETB X.Y
X is the port number P0, P1, P2, or P3
Y is the desired bit number from 0 to 7 for
data bits D0 to D7
ex. SETB P1.5 sets bit 5 of port 1 high


Notice that when code such as
BIT SETB P1.0 is assembled, it becomes
ADDRESSES SETB 90H
The bit address for I/O ports
I/O Port P0 are 80H to 87H
Bit Addresses P1 are 90H to 97H
(cont’) P2 are A0H to A7H
P3 are B0H to B7H

Single-Bit Addressability of Ports
P0 P1 P2 P3 Port Bit
P0.0 (80) P1.0 (90) P2.0 (A0) P3.0 (B0) D0
P0.1 P1.1 P2.1 P3.1 D1
P0.2 P1.2 P2.2 P3.2 D2
P0.3 P1.3 P2.3 P3.3 D3
P0.4 P1.4 P2.4 P3.4 D4
P0.5 P1.5 P2.5 P3.5 D5
P0.6 P1.6 P2.6 P3.6 D6
P0.7 (87) P1.7 (97) P2.7 (A7) P3.7 (B7) D7


Bit addresses 80 – F7H
SFR RAM Address (Byte and Bit) belong to SFR of P0,
BIT Byte Byte
TCON, P1, SCON, P2, etc

ADDRESSES address Bit address address Bit address
FF 98 9F 9E 9D 9C 9B 9A 99 98 SCON

F0 F7 F6 F5 F4 F3 F2 F1 F0 B
I/O Port 90 97 96 95 94 93 92 91 90 P1

Bit Addresses E0 E7 E6 E5 E4 E3 E2 E1 E0 ACC
8D not bit addressable TH1
(cont’) 8C not bit addressable TH0
D0 D7 D6 D5 D4 D3 D2 D1 D0 PSW
8B not bit addressable TL1
8A not bit addressable TL0
B8 -- -- -- BC BB BA B9 B8 IP 89 not bit addressable TMOD
88 8F 8E 8D 8C 8B 8A 89 88 TCON
B0 B7 B6 B5 B4 B3 B2 B1 B0 P3
87 not bit addressable PCON

A8 AF AE AD AC AB AA A9 A8 IE
83 not bit addressable DPH

A0 A7 A6 A5 A4 A3 A2 A1 A0 P2 82 not bit addressable DPL
81 not bit addressable SP
99 not bit addressable SBUF 80 87 86 85 84 83 82 81 80 P0

Special Function Register

Only registers A, B, PSW, IP, IE, ACC,
BIT SCON, and TCON are bit-addressable
ADDRESSES While all I/O ports are bit-addressable

Registers
In PSW register, two bits are set aside
Bit- for the selection of the register banks
Addressability Upon RESET, bank 0 is selected
We can select any other banks using the
bit-addressability of the PSW
CY AC -- RS1 RS0 OV -- P

RS1 RS0 Register Bank Address
0 0 0 00H - 07H
0 1 1 08H - 0FH
1 0 2 10H - 17H
1 1 3 18H - 1FH


Example 5-13
Write a program to save the accumulator in R7 of bank 2.
BIT Solution:
ADDRESSES CLR PSW.3
SETB PSW.4
MOV R7,A
Registers Example 5-14
Bit- While there are instructions such as JNC and JC to check the carry flag
Addressability bit (CY), there are no such instructions for the overflow flag bit (OV).
(cont’) How would you write code to check OV?
Solution:
JB PSW.2,TARGET ;jump if OV=1

CY AC -- RS1 RS0 OV -- P

Example 5-18
While a program to save the status of bit P1.7 on RAM address bit 05.
Solution:
MOV C,P1.7
MOV 05,C


Example 5-15
BIT Write a program to see if the RAM location 37H contains an even
ADDRESSES value. If so, send it to P2. If not, make it even and then send it to P2.
Solution:
MOV A,37H ;load RAM 37H into ACC
Registers JNB ACC.0,YES ;if D0 of ACC 0? If so jump
Bit- INC A ;it’s odd, make it even
YES: MOV P2,A ;send it to P2
Addressability
Example 5-17
(cont’)

The status of bits P1.2 and P1.3 of I/O port P1 must be saved before
they are changed. Write a program to save the status of P1.2 in bit
location 06 and the status of P1.3 in bit location 07
Solution:
CLR 06 ;clear bit addr. 06
CLR 07 ;clear bit addr. 07
JNB P1.2,OVER ;check P1.2, if 0 then jump
SETB 06 ;if P1.2=1,set bit 06 to 1
OVER: JNB P1.3,NEXT ;check P1.3, if 0 then jump
SETB 07 ;if P1.3=1,set bit 07 to 1
NEXT: ...


The BIT directive is a widely used
BIT
ADDRESSES
directive to assign the bit-addressable
I/O and RAM locations
Using BIT Allow a program to assign the I/O or RAM
bit at the beginning of the program,
making it easier to modify them
Example 5-22

A switch is connected to pin P1.7 and an LED to pin P2.0. Write a
program to get the status of the switch and send it to the LED.
Solution:
LED BIT P1.7 ;assign bit
SW BIT P2.0 ;assign bit
HERE: MOV C,SW ;get the bit from the port
MOV LED,C ;send the bit to the port
SJMP HERE ;repeat forever


Example 5-20
BIT
Assume that bit P2.3 is an input and represents the condition of an
ADDRESSES oven. If it goes high, it means that the oven is hot. Monitor the bit
continuously. Whenever it goes high, send a high-to-low pulse to port
P1.5 to turn on a buzzer.
Using BIT
Solution:
(cont’)
OVEN_HOT BIT P2.3
BUZZER BIT P1.5
HERE: JNB OVEN_HOT,HERE ;keep monitoring
ACALL DELAY

CPL BUZZER ;sound the buzzer
ACALL DELAY
SJMP HERE


Use the EQU to assign addresses
BIT
ADDRESSES Defined by names, like P1.7 or P2
Defined by addresses, like 97H or 0A0H
Using EQU Example 5-24
of the switch and make the following decision.
(a) If SW = 0, send “0” to P2
(b) If SW = 1, send “1“ to P2

Solution: SW EQU 97H
MYDATA EQU 0A0H
SW EQU P1.7
MYDATA EQU P2
HERE: MOV C,SW
JC OVER
MOV MYDATA,#’0’
SJMP HERE
OVER: MOV MYDATA,#’1’
SJMP HERE
END


The 8052 has another 128 bytes of on-
EXTRA 128
BYTE ON-CHIP
chip RAM with addresses 80 – FFH
RAM IN 8052 It is often called upper memory
Use indirect addressing mode, which uses R0
and R1 registers as pointers with values of 80H
or higher
– MOV @R0, A and MOV @R1, A
The same address space assigned to the
SFRs
Use direct addressing mode
– MOV 90H, #55H is the same as
MOV P1, #55H


Example 5-27
EXTRA 128
Assume that the on-chip ROM has a message. Write a program to
BYTE ON-CHIP copy it from code space into the upper memory space starting at
RAM IN 8052 address 80H. Also, as you place a byte in upper RAM, give a copy to
P0.
(cont’)
Solution:
ORG 0
MOV DPTR,#MYDATA
MOV R1,#80H ;access the upper memory
B1: CLR A
MOVC A,@A+DPTR ;copy from code ROM
MOV @R1,A ;store in upper memory
MOV P0,A ;give a copy to P0
JZ EXIT ;exit if last byte
INC DPTR ;increment DPTR
INC R1 ;increment R1
SJMP B1 ;repeat until last byte
EXIT: SJMP $ ;stay here when finished
;---------------
ORG 300H
MYDATA: DB “The Promise of World Peace”,0
END


ARITHMETIC & LOGIC
INSTRUCTIONS AND
PROGRAMS


Chung-Ping Young
楊中平


ADD A,source ;A = A + source
ARITHMETIC The instruction ADD is used to add two
INSTRUCTIONS operands
Destination operand is always in register A
Addition of
Source operand can be a register,
Unsigned immediate data, or in memory
Numbers
Memory-to-memory arithmetic operations

are never allowed in 8051 Assembly
language
Show how the flag register is affected by the following instruction.
MOV A,#0F5H ;A=F5 hex CY =1, since there is a
ADD A,#0BH ;A=F5+0B=00 carry out from D7
PF =1, because the number
Solution:
of 1s is zero (an even
F5H 1111 0101 number), PF is set to 1.
+ 0BH + 0000 1011 AC =1, since there is a
100H 0000 0000 carry from D3 to D4


Assume that RAM locations 40 – 44H have the following values.
ARITHMETIC Write a program to find the sum of the values. At the end of the
INSTRUCTIONS program, register A should contain the low byte and R7 the high byte.
40 = (7D)
41 = (EB)
Addition of 42 = (C5)
Individual 43 = (5B)
44 = (30)
Bytes
Solution:
MOV R0,#40H ;load pointer
MOV R2,#5 ;load counter
CLR A ;A=0
MOV R7,A ;clear R7
AGAIN: ADD A,@R0 ;add the byte ptr to by R0
JNC NEXT ;if CY=0 don’t add carry
INC R7 ;keep track of carry
NEXT: INC R0 ;increment pointer
DJNZ R2,AGAIN ;repeat until R2 is zero


When adding two 16-bit data operands,
ARITHMETIC the propagation of a carry from lower
INSTRUCTIONS byte to higher byte is concerned
1 When the first byte is added
ADDC and 3C E7 (E7+8D=74, CY=1).
Addition of 16- + 3B 8D The carry is propagated to the
Bit Numbers 78 74 higher byte, which result in 3C
+ 3B + 1 =78 (all in hex)

Write a program to add two 16-bit numbers. Place the sum in R7 and
R6; R6 should have the lower byte.
Solution:
CLR C ;make CY=0
MOV A, #0E7H ;load the low byte now A=E7H
ADD A, #8DH ;add the low byte
MOV R6, A ;save the low byte sum in R6
MOV A, #3CH ;load the high byte
ADDC A, #3BH ;add with the carry
MOV R7, A ;save the high byte sum


The binary representation of the digits
ARITHMETIC 0 to 9 is called BCD (Binary Coded
INSTRUCTIONS Decimal) Digit BCD
0 0000
Unpacked BCD 1 0001
BCD Number In unpacked BCD, the lower 4 2 0010
System bits of the number represent the 3 0011
BCD number, and the rest of the 4 0100
bits are 0 5 0101

6 0110
Ex. 00001001 and 00000101 are 7 0111
unpacked BCD for 9 and 5 8 1000

Packed BCD 9 1001

In packed BCD, a single byte has
two BCD number in it, one in the
lower 4 bits, and one in the
upper 4 bits
Ex. 0101 1001 is packed BCD for
59H

ARITHMETIC Adding two BCD numbers must give a
INSTRUCTIONS BCD result Adding these two
numbers gives
Unpacked and MOV A, #17H 0011 1111B (3FH),
Which is not BCD!
Packed BCD ADD A, #28H

The result above should have been 17 + 28 = 45 (0100 0101).
To correct this problem, the programmer must add 6 (0110) to the
low digit: 3F + 06 = 45H.


DA A ;decimal adjust for addition
ARITHMETIC The DA instruction is provided to
INSTRUCTIONS correct the aforementioned problem
associated with BCD addition
DA Instruction
The DA instruction will add 6 to the lower
nibble or higher nibble if need

Example: 6CH
MOV A,#47H ;A=47H first BCD operand
MOV B,#25H ;B=25H second BCD operand
ADD A,B ;hex(binary) addition(A=6CH)
DA A ;adjust for BCD addition
(A=72H)
72H
DA works only
after an ADD, The “DA” instruction works only on A. In other word, while the source
but not after INC can be an operand of any addressing mode, the destination must be in
register A in order for DA to work.


Summary of DA instruction
ARITHMETIC After an ADD or ADDC instruction
INSTRUCTIONS 1. If the lower nibble (4 bits) is greater than 9, or
if AC=1, add 0110 to the lower 4 bits
DA Instruction 2. If the upper nibble is greater than 9, or if
(cont’) CY=1, add 0110 to the upper 4 bits

Example:
HEX BCD
29 0010 1001
+ 18 + 0001 1000
41 0100 0001 AC=1
+ 6 + 0110
47 0100 0111

Since AC=1 after the
addition, ”DA A” will add 6 to the
lower nibble.
The final result is in BCD format.

Assume that 5 BCD data items are stored in RAM locations starting
at 40H, as shown below. Write a program to find the sum of all the
ARITHMETIC numbers. The result must be in BCD.
INSTRUCTIONS 40=(71)
41=(11)
42=(65)
DA Instruction 43=(59)
(cont’) 44=(37)
Solution:
MOV R0,#40H ;Load pointer

MOV R2,#5 ;Load counter
CLR A ;A=0
MOV R7,A ;Clear R7
AGAIN: ADD A,@R0 ;add the byte pointer
;to by R0
DA A ;adjust for BCD
JNC NEXT ;if CY=0 don’t
;accumulate carry
INC R7 ;keep track of carries
NEXT: INC R0 ;increment pointer
DJNZ R2,AGAIN ;repeat until R2 is 0


In many microprocessor there are two
ARITHMETIC different instructions for subtraction:
INSTRUCTIONS SUB and SUBB (subtract with borrow)
In the 8051 we have only SUBB
Subtraction of
Unsigned The 8051 uses adder circuitry to perform
the subtraction
Numbers

SUBB A,source ;A = A – source – CY
To make SUB out of SUBB, we have to
make CY=0 prior to the execution of
the instruction
Notice that we use the CY flag for the
borrow


SUBB when CY = 0
ARITHMETIC 1. Take the 2’s complement of the
INSTRUCTIONS subtrahend (source operand)
2. Add it to the minuend (A)
Subtraction of 3. Invert the carry
Unsigned
CLR C
Numbers MOV A,#4C ;load A with value 4CH
(cont’) SUBB A,#6EH ;subtract 6E from A
JNC NEXT ;if CY=0 jump to NEXT
CPL A ;if CY=1, take 1’s complement
INC A ;and increment to get 2’s comp
NEXT: MOV R1,A ;save A in R1
2’s
Solution: complement
4C 0100 1100 0100 1100
CY=0, the result is positive; - 6E 0110 1110 1001 0010 +
CY=1, the result is negative
-22 01101 1110
and the destination has the CY =1
2’s complement of the result Invert carry


SUBB when CY = 1
ARITHMETIC
This instruction is used for multi-byte
INSTRUCTIONS numbers and will take care of the borrow
of the lower operand
Subtraction of A = 62H – 96H – 0 = CCH
Unsigned
CLR C CY = 1
MOV A,#62H ;A=62H
Numbers SUBB A,#96H ;62H-96H=CCH with CY=1
(cont’) MOV R7,A ;save the result
MOV A,#27H ;A=27H
SUBB A,#12H ;27H-12H-1=14H
MOV R6,A ;save the result
A = 27H - 12H - 1 = 14H
Solution: CY = 0
We have 2762H - 1296H = 14CCH.


The 8051 supports byte by byte
ARITHMETIC multiplication only
INSTRUCTIONS
The byte are assumed to be unsigned data
Unsigned MUL AB ;AxB, 16-bit result in B, A
Multiplication MOV A,#25H ;load 25H to reg. A
MOV B,#65H ;load 65H to reg. B

MUL AB ;25H * 65H = E99 where
;B = OEH and A = 99H

Unsigned Multiplication Summary (MUL AB)
Multiplication Operand1 Operand2 Result
Byte x byte A B B = high byte
A = low byte


The 8051 supports byte over byte
ARITHMETIC
INSTRUCTIONS
division only
The byte are assumed to be unsigned data
Unsigned DIV AB ;divide A by B, A/B
Division
MOV A,#95 ;load 95 to reg. A

MOV B,#10 ;load 10 to reg. B
MUL AB ;A = 09(quotient) and
;B = 05(remainder)

Unsigned Division Summary (DIV AB)
Division Numerator Denominator Quotient Remainder
Byte / byte A B A B

CY is always 0
If B ≠ 0, OV = 0
If B = 0, OV = 1 indicates error


(a) Write a program to get hex data in the range of 00 – FFH from
port 1 and convert it to decimal. Save it in R7, R6 and R5.
ARITHMETIC (b) Assuming that P1 has a value of FDH for data, analyze program.
INSTRUCTIONS Solution:
(a)
Application for
MOV A,#0FFH
MOV P1,A ;make P1 an input port
DIV MOV
MOV
A,P1
B,#10
;read data from P1
;B=0A hex
DIV AB ;divide by 10
MOV R7,B ;save lower digit
MOV B,#10
DIV AB ;divide by 10 once more
MOV R6,B ;save the next digit
MOV R5,A ;save the last digit
(b) To convert a binary (hex) value to decimal, we divide it by 10
repeatedly until the quotient is less than 10. After each division the
remainder is saves.
Q R
FD/0A = 19 3 (low digit)
19/0A = 2 5 (middle digit)
2 (high digit)
Therefore, we have FDH=253.

D7 (MSB) is the sign and D0 to D6 are
SIGNED the magnitude of the number
ARITHMETIC
If D7=0, the operand is positive, and if
INSTRUCTIONS D7=1, it is negative
D7 D6 D5 D4 D3 D2 D1 D0
Signed 8-bit
Operands
Sign Magnitude
Positive numbers are 0 to +127
Negative number representation (2’s
complement)
1. Write the magnitude of the number in 8-bit
binary (no sign)
2. Invert each bit
3. Add 1 to it

Show how the 8051 would represent -34H

SIGNED Solution:
0011 0100 34H given in binary
ARITHMETIC
1.

1100 1011 invert each bit
INSTRUCTIONS
2.

3. 1100 1100 add 1 (which is CC in hex)
Signed number representation of -34 in 2’s complement is CCH
Signed 8-bit
Operands Decimal Binary Hex
(cont’) -128 1000 0000 80
-127 1000 0001 81
-126 1000 0010 82
... ... ... ...
-2 1111 1110 FE
-1 1111 1111 FF
0 0000 0000 00
+1 0000 0001 01
+2 0000 0010 02
... ... ... ...
+127 0111 1111 7F

If the result of an operation on signed
SIGNED numbers is too large for the register
ARITHMETIC
INSTRUCTIONS An overflow has occurred and the
programmer must be noticed
Overflow Examine the following code and analyze the result.
Problem MOV A,#+96 ;A=0110 0000 (A=60H)
MOV R1,#+70 ;R1=0100 0110(R1=46H)
ADD A,R1 ;A=1010 0110
;A=A6H=-90,INVALID
Solution:
+96 0110 0000
+ +70 0100 0110
+ 166 1010 0110 and OV =1
According to the CPU, the result is -90, which is wrong. The CPU
sets OV=1 to indicate the overflow


In 8-bit signed number operations,
SIGNED
ARITHMETIC
OV is set to 1 if either occurs:
INSTRUCTIONS 1. There is a carry from D6 to D7, but no
carry out of D7 (CY=0)
OV Flag 2. There is a carry from D7 out (CY=1), but
no carry from D6 to D7
MOV A,#-128 ;A=1000 0000(A=80H)
MOV R4,#-2 ;R4=1111 1110(R4=FEH)
ADD A,R4 ;A=0111 1110(A=7EH=+126,INVALID)
-128 1000 0000
+ -2 1111 1110
-130 0111 1110 and OV=1

OV = 1
The result +126 is wrong


MOV A,#-2 ;A=1111 1110(A=FEH)
MOV R1,#-5 ;R1=1111 1011(R1=FBH)
SIGNED ADD A,R1 ;A=1111 1001(A=F9H=-7,
ARITHMETIC ;Correct, OV=0)
INSTRUCTIONS -2 1111 1110
+ -5 1111 1011
OV Flag -7 1111 1001 and OV=0

(cont’)
OV = 0
The result -7 is correct
MOV A,#+7 ;A=0000 0111(A=07H)
MOV R1,#+18 ;R1=0001 0010(R1=12H)
ADD A,R1 ;A=0001 1001(A=19H=+25,
;Correct,OV=0)
7 0000 0111
+ 18 0001 0010
25 0001 1001 and OV=0
OV = 0
The result +25 is correct

In unsigned number addition, we must
SIGNED
ARITHMETIC
monitor the status of CY (carry)
INSTRUCTIONS Use JNC or JC instructions
In signed number addition, the OV
OV Flag (overflow) flag must be monitored by
(cont’)
the programmer

JB PSW.2 or JNB PSW.2


To make the 2’s complement of a
SIGNED
ARITHMETIC
number
INSTRUCTIONS
CPL A ;1’s complement (invert)
ADD A,#1 ;add 1 to make 2’s comp.
2's
Complement


ANL destination,source
LOGIC AND ;dest = dest AND source
COMPARE
This instruction will perform a logic
INSTRUCTIONS
AND on the two operands and place
AND
the result in the destination
The destination is normally the
accumulator
The source operand can be a register, in
memory, or immediate

X Y X AND Y Show the results of the following.
0 0 0 MOV A,#35H ;A = 35H
0 1 0 ANL A,#0FH ;A = A AND 0FH
1 0 0 35H 0 0 1 1 0 1 0 1 ANL is often used to
0FH 0 0 0 0 1 1 1 1 mask (set to 0) certain
1 1 1
05H 0 0 0 0 0 1 0 1 bits of an operand


ORL destination,source
LOGIC AND ;dest = dest OR source
COMPARE The destination and source operands
INSTRUCTIONS are ORed and the result is placed in
the destination
OR
accumulator

X Y X OR Y Show the results of the following.
0 0 0 MOV A,#04H ;A = 04
0 1 1 ORL A,#68H ;A = 6C
ORL instruction can be
1 0 1 04H 0 0 0 0 0 1 0 0 used to set certain bits
1 1 1
68H 0 1 1 0 1 0 0 0 of an operand to 1
6CH 0 1 1 0 1 1 0 0


XRL destination,source
LOGIC AND ;dest = dest XOR source
COMPARE
INSTRUCTIONS
This instruction will perform XOR
operation on the two operands and
XOR place the result in the destination

accumulator
X Y X XOR Y Show the results of the following.
0 0 0 MOV A,#54H
0 1 1 XRL A,#78H
XRL instruction can be
1 0 1 54H 0 1 0 1 0 1 0 0 used to toggle certain
1 1 0 78H 0 1 1 1 1 0 0 0 bits of an operand
2CH 0 0 1 0 1 1 0 0

The XRL instruction can be used to clear the contents of a register by
LOGIC AND XORing it with itself. Show how XRL A,A clears A, assuming that
COMPARE AH = 45H.

INSTRUCTIONS 45H 0 1 0 0 0 1 0 1
45H 0 1 0 0 0 1 0 1
00H 0 0 0 0 0 0 0 0
XOR
(cont’) Read and test P1 to see whether it has the value 45H. If it does, send
99H to P2; otherwise, it stays cleared.
XRL can be used to
Solution: see if two registers
MOV P2,#00 ;clear P2 have the same value
MOV P1,#0FFH ;make P1 an input port
MOV R3,#45H ;R3=45H
MOV A,P1 ;read P1
XRL A,R3
JNZ EXIT ;jump if A is not 0
MOV P2,#99H
EXIT: ... If both registers have the same
value, 00 is placed in A. JNZ
and JZ test the contents of the
accumulator.

CPL A ;complements the register A
LOGIC AND
COMPARE This is called 1’s complement
INSTRUCTIONS MOV A, #55H
CPL A ;now A=AAH
Complement ;0101 0101(55H)
;becomes 1010 1010(AAH)
Accumulator
To get the 2’s complement, all we
have to do is to to add 1 to the 1’s
complement


CJNE destination,source,rel. addr.
LOGIC AND
COMPARE The actions of comparing and jumping
INSTRUCTIONS are combined into a single instruction
called CJNE (compare and jump if not
Compare equal)
Instruction
The CJNE instruction compares two

operands, and jumps if they are not equal
The destination operand can be in the
accumulator or in one of the Rn registers
The source operand can be in a register, in
The operands themselves remain unchanged
It changes the CY flag to indicate if the
destination operand is larger or smaller

CJNE R5,#80,NOT_EQUAL ;check R5 for 80
LOGIC AND ... ;R5 = 80
COMPARE NOT_EQUAL:
INSTRUCTIONS JNC NEXT ;jump if R5 > 80
... ;R5 < 80
NEXT: ...
Compare
Instruction Compare Carry Flag
(cont’)

destination ≥ source CY = 0
destination < source CY = 1
CY flag is always
checked for cases
of greater or less Notice in the CJNE instruction that any
than, but only after Rn register can be compared with an
it is determined that immediate value
they are not equal
There is no need for register A to be
involved


The compare instruction is really a
LOGIC AND subtraction, except that the operands
COMPARE remain unchanged
INSTRUCTIONS Flags are changed according to the
execution of the SUBB instruction
Compare Write a program to read the temperature and test it for the value 75.
Instruction According to the test results, place the temperature value into the
registers indicated by the following.
(cont’) If T = 75 then A = 75
If T < 75 then R1 = T
If T > 75 then R2 = T
Solution:
MOV A,P1 ;read P1 port
CJNE A,#75,OVER ;jump if A is not 75
SJMP EXIT ;A=75, exit
OVER: JNC NEXT ;if CY=0 then A>75
MOV R1,A ;CY=1, A<75, save in R1
SJMP EXIT ; and exit
NEXT: MOV R2,A ;A>75, save it in R2
EXIT: ...


RR A ;rotate right A
ROTATE
INSTRUCTION In rotate right
AND DATA The 8 bits of the accumulator are rotated
SERIALIZATION right one bit, and
Bit D0 exits from the LSB and enters into
Rotating Right MSB, D7
and Left

MSB LSB

MOV A,#36H ;A = 0011 0110
RR A ;A = 0001 1011
RR A ;A = 1000 1101
RR A ;A = 1100 0110
RR A ;A = 0110 0011


RL A ;rotate left A
ROTATE
INSTRUCTION In rotate left
AND DATA The 8 bits of the accumulator are rotated
SERIALIZATION left one bit, and
Bit D7 exits from the MSB and enters into
Rotating Right LSB, D0
and Left
(cont’)
MSB LSB

MOV A,#72H ;A = 0111 0010
RL A ;A = 1110 0100
RL A ;A = 1100 1001


RRC A ;rotate right through carry
ROTATE
INSTRUCTION In RRC A
AND DATA Bits are rotated from left to right
SERIALIZATION They exit the LSB to the carry flag, and
the carry flag enters the MSB
Rotating
through Carry
MSB LSB CY

CLR C ;make CY = 0
MOV A,#26H ;A = 0010 0110
RRC A ;A = 0001 0011 CY = 0
RRC A ;A = 0000 1001 CY = 1
RRC A ;A = 1000 0100 CY = 1


RLC A ;rotate left through carry
ROTATE
INSTRUCTION In RLC A
AND DATA Bits are shifted from right to left
SERIALIZATION They exit the MSB and enter the carry flag,
and the carry flag enters the LSB
Rotating
through Carry
(cont’) CY MSB LSB

Write a program that finds the number of 1s in a given byte.
MOV R1,#0
MOV R7,#8 ;count=08
MOV A,#97H
AGAIN: RLC A
JNC NEXT ;check for CY
INC R1 ;if CY=1 add to count
NEXT: DJNZ R7,AGAIN


Serializing data is a way of sending a
ROTATE
INSTRUCTION byte of data one bit at a time through
AND DATA a single pin of microcontroller
SERIALIZATION Using the serial port, discussed in Chapter
10
Serializing Data To transfer data one bit at a time and
control the sequence of data and spaces
in between them


Transfer a byte of data serially by
ROTATE
INSTRUCTION Moving CY to any pin of ports P0 – P3
AND DATA Using rotate instruction
SERIALIZATION Write a program to transfer value 41H serially (one bit at a time)
via pin P2.1. Put two highs at the start and end of the data. Send the
byte LSB first.
Serializing Data
Solution:
(cont’) MOV A,#41H
SETB P2.1 ;high
SETB P2.1 ;high
MOV R5,#8
AGAIN: RRC A
MOV P2.1,C ;send CY to P2.1
DJNZ R5,HERE
SETB P2.1 ;high
SETB P2.1 ;high
Pin
Register A CY P2.1
D7 D0

Write a program to bring in a byte of data serially one bit at a time
ROTATE via pin P2.7 and save it in register R2. The byte comes in with the
INSTRUCTION LSB first.
AND DATA Solution:
SERIALIZATION MOV R5,#8
AGAIN: MOV C,P2.7 ;bring in bit
RRC A
Serializing Data DJNZ R5,HERE
(cont’) MOV R2,A ;save it
Pin
P2.7 CY Register A
D7 D0


There are several instructions by which
ROTATE
INSTRUCTION the CY flag can be manipulated directly
AND DATA Instruction Function
SERIALIZATION SETB C Make CY = 1
CLR C Clear carry bit (CY = 0)
Single-bit CPL C Complement carry bit
Operations with MOV b,C Copy carry status to bit location (CY = b)
Copy bit location status to carry (b = CY)
CY
MOV C,b
JNC target Jump to target if CY = 0
JC target Jump to target if CY = 1
ANL C,bit AND CY with bit and save it on CY
ANL C,/bit AND CY with inverted bit and save it on CY
ORL C,bit OR CY with bit and save it on CY
ORL C,/bit OR CY with inverted bit and save it on CY


Assume that bit P2.2 is used to control an outdoor light and bit P2.5
ROTATE a light inside a building. Show how to turn on the outside light and
INSTRUCTION turn off the inside one.
AND DATA Solution:
SERIALIZATION SETB C ;CY = 1
ORL C,P2.2 ;CY = P2.2 ORed w/ CY
MOV P2.2,C ;turn it on if not on
Single-bit CLR C ;CY = 0
Operations with ANL C,P2.5 ;CY = P2.5 ANDed w/ CY

MOV P2.5,C ;turn it off if not off
CY
(cont’) Write a program that finds the number of 1s in a given byte.
Solution:
MOV R1,#0 ;R1 keeps number of 1s
MOV R7,#8 ;counter, rotate 8 times
MOV A,#97H ;find number of 1s in 97H
AGAIN: RLC A ;rotate it thru CY
JNC NEXT ;check CY
INC R1 ;if CY=1, inc count
NEXT: DJNZ R7,AGAIN ;go thru 8 times


SWAP A
ROTATE
INSTRUCTION It swaps the lower nibble and the
AND DATA higher nibble
SERIALIZATION In other words, the lower 4 bits are put
into the higher 4 bits and the higher 4 bits
SWAP are put into the lower 4 bits
SWAP works only on the accumulator
(A)
before : D7-D4 D3-D0

after : D3-D0 D7-D4


(a) Find the contents of register A in the following code.
ROTATE (b) In the absence of a SWAP instruction, how would you
INSTRUCTION exchange the nibbles? Write a simple program to show the
AND DATA process.
SERIALIZATION Solution:
(a)
SWAP MOV A,#72H ;A = 72H
(cont’) SWAP A ;A = 27H
(b)
MOV A,#72H ;A = 0111 0010
RL A ;A = 0111 0010
RL A ;A = 0111 0010
RL A ;A = 0111 0010
RL A ;A = 0111 0010


BCD AND ASCII ASCII code and BCD for digits 0 - 9
APPLICATION Key ASCII (hex) Binary BCD (unpacked)

PROGRAMS 0 30 011 0000 0000 0000
1 31 011 0001 0000 0001
2 32 011 0010 0000 0010
3 33 011 0011 0000 0011
4 34 011 0100 0000 0100
5 35 011 0101 0000 0101
6 36 011 0110 0000 0110
7 37 011 0111 0000 0111
8 38 011 1000 0000 1000
9 39 011 1001 0000 1001


The DS5000T microcontrollers have a
BCD AND ASCII real-time clock (RTC)
APPLICATION
PROGRAMS
The RTC provides the time of day (hour,
minute, second) and the date (year,
month, day) continuously, regardless of
Packed BCD to whether the power is on or off
ACSII
Conversion
However this data is provided in
packed BCD
To be displayed on an LCD or printed by
the printer, it must be in ACSII format
Packed BCD Unpacked BCD ASCII

29H 02H & 09H 32H & 39H
0010 1001 0000 0010 & 0011 0010 &
0000 1001 0011 1001


To convert ASCII to packed BCD
BCD AND ASCII
APPLICATION It is first converted to unpacked BCD (to
PROGRAMS get rid of the 3)
Combined to make packed BCD
ASCII to
key ASCII Unpacked BCD Packed BCD
Packed BCD
Conversion 4 34 0000 0100
7 37 0000 0111 0100 0111 or 47H

MOV A, #’4’ ;A=34H, hex for ‘4’
MOV R1,#’7’ ;R1=37H,hex for ‘7’
ANL A, #0FH ;mask upper nibble (A=04)
ANL R1,#0FH ;mask upper nibble (R1=07)
SWAP A ;A=40H
ORL A, R1 ;A=47H, packed BCD


Assume that register A has packed BCD, write a program to convert
BCD AND ASCII packed BCD to two ASCII numbers and place them in R2 and R6.
APPLICATION
MOV A,#29H ;A=29H, packed BCD
PROGRAMS MOV R2,A ;keep a copy of BCD data
ANL A,#0FH ;mask the upper nibble (A=09)
ASCII to ORL A,#30H ;make it an ASCII, A=39H(‘9’)
MOV R6,A ;save it
Packed BCD MOV A,R2 ;A=29H, get the original
Conversion data
(cont’) ANL A,#0F0H ;mask the lower nibble
RR A ;rotate right
RR A ;rotate right
RR A ;rotate right SWAP A
RR A ;rotate right
ORL A,#30H ;A=32H, ASCII char. ’2’
MOV R2,A ;save ASCII char in R2


Assume that the lower three bits of P1 are connected to three
BCD AND ASCII switches. Write a program to send the following ASCII characters
APPLICATION to P2 based on the status of the switches.
PROGRAMS 000 ‘0’
001 ‘1’
010 ‘2’
Using a Look- 011 ‘3’
100 ‘4’
up Table for 101 ‘5’
ASCII 110 ‘6’
111 ‘7’
Solution:
MOV DPTR,#MYTABLE
MOV A,P1 ;get SW status
ANL A,#07H ;mask all but lower 3
MOVC A,@A+DPTR ;get data from table
MOV P2,A ;display value
SJMP $ ;stay here
;------------------
ORG 400H
MYTABLE DB ‘0’,‘1’,‘2’,‘3’,‘4’,‘5’,‘6’,‘7’
END


To ensure the integrity of the ROM
BCD AND ASCII
APPLICATION contents, every system must perform
PROGRAMS the checksum calculation
The process of checksum will detect any
Checksum Byte corruption of the contents of ROM
in ROM The checksum process uses what is called
a checksum byte
The checksum byte is an extra byte that is
tagged to the end of series of bytes of data


To calculate the checksum byte of a
BCD AND ASCII
APPLICATION series of bytes of data
PROGRAMS Add the bytes together and drop the
carries
Checksum Byte Take the 2’s complement of the total sum,
in ROM and it becomes the last byte of the series
(cont’)

To perform the checksum operation,
add all the bytes, including the
checksum byte
The result must be zero
If it is not zero, one or more bytes of data
have been changed


Assume that we have 4 bytes of hexadecimal data: 25H, 62H, 3FH, and
52H.(a) Find the checksum byte, (b) perform the checksum operation to
BCD AND ASCII ensure data integrity, and (c) if the second byte 62H has been changed
APPLICATION to 22H, show how checksum detects the error.

PROGRAMS
Solution:
(a) Find the checksum byte.
25H The checksum is calculated by first adding the
+ 62H bytes. The sum is 118H, and dropping the carry,
Checksum Byte +
+
3FH
52H
we get 18H. The checksum byte is the 2’s
complement of 18H, which is E8H
in ROM 118H
(b) Perform the checksum operation to ensure data integrity.
(cont’) 25H
+ 62H Adding the series of bytes including the checksum
+ 3FH byte must result in zero. This indicates that all the
+ 52H bytes are unchanged and no byte is corrupted.
+ E8H
200H (dropping the carries)
(c) If the second byte 62H has been changed to 22H, show how
checksum detects the error.
25H
+ 3FH byte shows that the result is not zero, which indicates
+ 52H that one or more bytes have been corrupted.
+ E8H
1C0H (dropping the carry, we get C0H)


Many ADC (analog-to-digital converter)
BCD AND ASCII
APPLICATION chips provide output data in binary
PROGRAMS (hex)
To display the data on an LCD or PC
Binary (Hex) screen, we need to convert it to ASCII
to ASCII Convert 8-bit binary (hex) data to decimal
Conversion digits, 000 – 255
Convert the decimal digits to ASCII digits,
30H – 39H


8051 PROGRAMMING IN C


Chung-Ping Young
楊中平


Compilers produce hex files that is
WHY downloaded to ROM of microcontroller
PROGRAM
The size of hex file is the main concern
8051 IN C
Microcontrollers have limited on-chip ROM
Code space for 8051 is limited to 64K bytes
C programming is less time consuming,
but has larger hex file size
The reasons for writing programs in C

It is easier and less time consuming to
write in C than Assembly
C is easier to modify and update
You can use code available in function
libraries
C code is portable to other microcontroller
with little of no modification

A good understanding of C data types
DATA TYPES
for 8051 can help programmers to
create smaller hex files
Unsigned char
Signed char
Unsigned int
Signed int
Sbit (single bit)
Bit and sfr


The character data type is the most
DATA TYPES
natural choice
Unsigned char 8051 is an 8-bit microcontroller
Unsigned char is an 8-bit data type in
the range of 0 – 255 (00 – FFH)
One of the most widely used data types
for the 8051
Counter value
ASCII characters
C compilers use the signed char as the
default if we do not put the keyword
unsigned


Write an 8051 C program to send values 00 – FF to port P1.
Solution:
DATA TYPES 1. Pay careful attention to
#include <reg51.h> the size of the data
void main(void) 2. Try to use unsigned char
Unsigned char { instead of int if possible
(cont’) unsigned char z;
for (z=0;z<=255;z++)
P1=z;
}

Write an 8051 C program to send hex values for ASCII characters of
0, 1, 2, 3, 4, 5, A, B, C, and D to port P1.
Solution:
#include <reg51.h>
void main(void)
{
unsigned char mynum[]=“012345ABCD”;
unsigned char z;
for (z=0;z<=10;z++)
P1=mynum[z];
}


DATA TYPES Write an 8051 C program to toggle all the bits of P1 continuously.
Solution:
Unsigned char //Toggle P1 forever
(cont’) #include <reg51.h>
void main(void)
{
for (;;)
{
p1=0x55;
p1=0xAA;
}
}


The signed char is an 8-bit data type
DATA TYPES Use the MSB D7 to represent – or +
Give us values from –128 to +127
Signed char We should stick with the unsigned char
unless the data needs to be
represented as signed numbers
temperature
Write an 8051 C program to send values of –4 to +4 to port P1.
Solution:
//Singed numbers
#include <reg51.h>
void main(void)
{
char mynum[]={+1,-1,+2,-2,+3,-3,+4,-4};
unsigned char z;
for (z=0;z<=8;z++)
P1=mynum[z];
}

The unsigned int is a 16-bit data type
DATA TYPES
Takes a value in the range of 0 to 65535
Unsigned and (0000 – FFFFH)
Signed int Define 16-bit variables such as memory
addresses
Set counter values of more than 256
Since registers and memory accesses are
in 8-bit chunks, the misuse of int variables
will result in a larger hex file
Signed int is a 16-bit data type
Use the MSB D15 to represent – or +
We have 15 bits for the magnitude of the
number from –32768 to +32767


DATA TYPES Write an 8051 C program to toggle bit D0 of the port P1 (P1.0)
50,000 times.
Single Bit Solution:
sbit keyword allows access to the
(cont’) #include <reg51.h> single bits of the SFR registers
sbit MYBIT=P1^0;

void main(void)
{
unsigned int z;
for (z=0;z<=50000;z++)
{
MYBIT=0;
MYBIT=1;
}
}


The bit data type allows access to
DATA TYPES
single bits of bit-addressable memory
Bit and sfr spaces 20 – 2FH
To access the byte-size SFR registers,
we use the sfr data type
Data Type Size in Bits Data Range/Usage
unsigned char 8-bit 0 to 255
(signed) char 8-bit -128 to +127
unsigned int 16-bit 0 to 65535
(signed) int 16-bit -32768 to +32767
sbit 1-bit SFR bit-addressable only
bit 1-bit RAM bit-addressable only
sfr 8-bit RAM addresses 80 – FFH only


There are two way s to create a time
TIME DELAY delay in 8051 C
Using the 8051 timer (Chap. 9)
Using a simple for loop
be mindful of three factors that can affect
the accuracy of the delay
The 8051 design
– The number of machine cycle
– The number of clock periods per machine
cycle
The crystal frequency connected to the X1 – X2
input pins
Compiler choice
– C compiler converts the C statements and
functions to Assembly language instructions
– Different compilers produce different code


TIME DELAY Write an 8051 C program to toggle bits of P1 continuously forever
(cont’) with some delay.
Solution:
//Toggle P1 forever with some delay in between
//“on” and “off”
#include <reg51.h> We must use the oscilloscope to
void main(void)
measure the exact duration
{
unsigned int x;
for (;;) //repeat forever
{
p1=0x55;
for (x=0;x<40000;x++); //delay size
//unknown
p1=0xAA;
for (x=0;x<40000;x++);
}
}


TIME DELAY Write an 8051 C program to toggle bits of P1 ports continuously with
(cont’) a 250 ms.
Solution:
#include <reg51.h>
void MSDelay(unsigned int);
void main(void)
{
while (1) //repeat forever
{
p1=0x55;
MSDelay(250);
p1=0xAA;
MSDelay(250);
}
}
void MSDelay(unsigned int itime)
{
unsigned int i,j;
for (i=0;i<itime;i++)
for (j=0;j<1275;j++);
}

I/O LEDs are connected to bits P1 and P2. Write an 8051 C program that
PROGRAMMING shows the count from 0 to FFH (0000 0000 to 1111 1111 in binary)
on the LEDs.

Byte Size I/O Solution:
#include <reg51.h> Ports P0 – P3 are byte-accessable
#defind LED P2; and we use the P0 – P3 labels as
defined in the 8051/52 header file.
void main(void)
{
P1=00; //clear P1
LED=0; //clear P2
for (;;) //repeat forever
{
P1++; //increment P1
LED++; //increment P2
}
}


I/O Write an 8051 C program to get a byte of data form P1, wait 1/2
PROGRAMMING second, and then send it to P2.
Solution:
Byte Size I/O #include <reg51.h>
(cont’) void MSDelay(unsigned int);

void main(void)
{
unsigned char mybyte;
P1=0xFF; //make P1 input port
while (1)
{
mybyte=P1; //get a byte from P1
MSDelay(500);
P2=mybyte; //send it to P2
}
}


I/O Write an 8051 C program to get a byte of data form P0. If it is less
PROGRAMMING than 100, send it to P1; otherwise, send it to P2.
Solution:
Byte Size I/O #include <reg51.h>
(cont’)
void main(void)
{
P0=0xFF; //make P0 input port
while (1)
{
mybyte=P0; //get a byte from P0
if (mybyte<100)
else
}
}


I/O Write an 8051 C program to toggle only bit P2.4 continuously without
PROGRAMMING disturbing the rest of the bits of P2.
Ports P0 – P3 are bit-
Solution:
addressable and we use
Bit-addressable //Toggling an individual bit sbit data type to access
I/O #include <reg51.h>
sbit mybit=P2^4;
a single bit of P0 - P3

void main(void) Use the Px^y format, where
{ x is the port 0, 1, 2, or 3 and
while (1) y is the bit 0 – 7 of that port
{
mybit=1; //turn on P2.4
mybit=0; //turn off P2.4
}
}


I/O Write an 8051 C program to monitor bit P1.5. If it is high, send 55H
PROGRAMMING to P0; otherwise, send AAH to P2.
Solution:
Bit-addressable #include <reg51.h>
I/O sbit mybit=P1^5;
(cont’) void main(void)
{
mybit=1; //make mybit an input
while (1)
{
if (mybit==1)
P0=0x55;
else
P2=0xAA;
}
}


A door sensor is connected to the P1.1 pin, and a buzzer is connected
to P1.7. Write an 8051 C program to monitor the door sensor, and
I/O when it opens, sound the buzzer. You can sound the buzzer by
PROGRAMMING sending a square wave of a few hundred Hz.
Solution:
I/O sbit Dsensor=P1^1;
(cont’) sbit Buzzer=P1^7;
void main(void)
{
Dsensor=1; //make P1.1 an input
while (1)
{
while (Dsensor==1)//while it opens
{
Buzzer=0;
MSDelay(200);
Buzzer=1;
MSDelay(200);
}
}
}

The data pins of an LCD are connected to P1. The information is
I/O latched into the LCD whenever its Enable pin goes from high to low.
Write an 8051 C program to send “The Earth is but One Country” to
PROGRAMMING this LCD.
Solution:
I/O #define LCDData P1 //LCDData declaration
(cont’) sbit En=P2^0; //the enable pin

void main(void)
{
unsigned char message[]
=“The Earth is but One Country”;
unsigned char z;
for (z=0;z<28;z++) //send 28 characters
{
LCDData=message[z];
En=1; //a high-
En=0; //-to-low pulse to latch data
}
}


Write an 8051 C program to toggle all the bits of P0, P1, and P2
continuously with a 250 ms delay. Use the sfr keyword to declare the
I/O port addresses. Another way to access the SFR RAM
PROGRAMMING Solution: space 80 – FFH is to use the sfr data type
//Accessing Ports as SFRs using sfr data type
Accessing SFR sfr P0=0x80;
sfr P1=0x90;
Addresses sfr P2=0xA0;
80 - FFH
void main(void)
{
while (1)
{
P0=0x55;
P1=0x55;
P2=0x55;
MSDelay(250);
P0=0xAA;
P1=0xAA;
P2=0xAA;
MSDelay(250);
}
}


I/O Write an 8051 C program to turn bit P1.5 on and off 50,000 times.
PROGRAMMING Solution: We can access a single bit of any
sbit MYBIT=0x95; SFR if we specify the bit address
Accessing SFR
Addresses void main(void)
{
80 - FFH unsigned int z;
(cont’) for (z=0;z<50000;z++)
{
MYBIT=1;
MYBIT=0;
}
}

Notice that there is no #include <reg51.h>.
This allows us to access any byte of the SFR RAM
space 80 – FFH. This is widely used for the new
generation of 8051 microcontrollers.


I/O Write an 8051 C program to get the status of bit P1.0, save it, and
PROGRAMMING send it to P2.7 continuously.
Solution:
Using bit Data #include <reg51.h>
Type for sbit inbit=P1^0;
sbit outbit=P2^7;
Bit-addressable bit membit; //use bit to declare
RAM //bit- addressable memory
We use bit data type to access
void main(void)
{ data in a bit-addressable section
while (1) of the data RAM space 20 – 2FH
{
membit=inbit; //get a bit from P1.0
outbit=membit; //send it to P2.7
}
}


Logical operators
LOGIC
OPERATIONS AND (&&), OR (||), and NOT (!)
Bit-wise operators
Bit-wise AND (&), OR (|), EX-OR (^), Inverter (~),
Operators in C Shift Right (>>), and Shift Left (<<)
These operators are widely used in software
engineering for embedded systems and control

Bit-wise Logic Operators for C
AND OR EX-OR Inverter
A B A&B A|B A^B ~B
0 0 0 0 0 1
0 1 0 1 1 0
1 0 0 1 1
1 1 1 1 0


LOGIC Run the following program on your simulator and examine the results.
OPERATIONS Solution:
#include <reg51.h>
Bit-wise
Operators in C void main(void)
{
(cont’) P0=0x35 & 0x0F; //ANDing
P1=0x04 | 0x68; //ORing
P2=0x54 ^ 0x78; //XORing
P0=~0x55; //inversing
P1=0x9A >> 3; //shifting right 3
P2=0x77 >> 4; //shifting right 4
P0=0x6 << 4; //shifting left 4
}


LOGIC Write an 8051 C program to toggle all the bits of P0 and P2
OPERATIONS continuously with a 250 ms delay. Using the inverting and Ex-OR
operators, respectively.

Bit-wise Solution:

Operators in C #include <reg51.h>
(cont’)
void main(void)
{
P0=0x55;
P2=0x55;
while (1)
{
P0=~P0;
P2=P2^0xFF;
MSDelay(250);
}
}


LOGIC Write an 8051 C program to get bit P1.0 and send it to P2.7 after
OPERATIONS inverting it.
Solution:
Bit-wise #include <reg51.h>
Operators in C sbit inbit=P1^0;
sbit outbit=P2^7;
(cont’) bit membit;

void main(void)
{
while (1)
{
membit=inbit; //get a bit from P1.0
outbit=~membit; //invert it and send
//it to P2.7
}
}


LOGIC Write an 8051 C program to read the P1.0 and P1.1 bits and issue an
OPERATIONS ASCII character to P0 according to the following table.
P1.1 P1.0
0 0 send ‘0’ to P0
Bit-wise 0 1 send ‘1’ to P0
Operators in C 1 0 send ‘2’ to P0
(cont’) 1 1 send ‘3’ to P0
Solution:
#include <reg51.h>

void main(void)
{
unsignbed char z;
z=P1;
z=z&0x3;

...


...
LOGIC switch (z)
{
OPERATIONS case(0):
{
P0=‘0’;
Bit-wise }
break;
Operators in C case(1):
(cont’) {
P0=‘1’;
break;
}
case(2):
{
P0=‘2’;
break;
}
case(3):
{
P0=‘3’;
break;
}
}
}


DATA Write an 8051 C program to convert packed BCD 0x29 to ASCII and
CONVERSION display the bytes on P1 and P2.
Solution:
Packed BCD to #include <reg51.h>
ASCII void main(void)
Conversion {
unsigned char x,y,z;
unsigned char mybyte=0x29;
x=mybyte&0x0F;
P1=x|0x30;
y=mybyte&0xF0;
y=y>>4;
P2=y|0x30;
}


DATA Write an 8051 C program to convert ASCII digits of ‘4’ and ‘7’ to
CONVERSION packed BCD and display them on P1.
Solution:
ASCII to #include <reg51.h>
Packed BCD void main(void)
Conversion {
unsigned char bcdbyte;
unsigned char w=‘4’;
unsigned char z=‘7’;
w=w&0x0F;
w=w<<4;
z=z&0x0F;
bcdbyte=w|z;
P1=bcdbyte;
}


DATA Write an 8051 C program to calculate the checksum byte for the data
25H, 62H, 3FH, and 52H.
CONVERSION
Solution:

Checksum Byte #include <reg51.h>

in ROM void main(void)
{
unsigned char mydata[]={0x25,0x62,0x3F,0x52};
unsigned char sum=0;
unsigned char x;
unsigned char chksumbyte;
for (x=0;x<4;x++)
{
P2=mydata[x];
sum=sum+mydata[x];
P1=sum;
}
chksumbyte=~sum+1;
P1=chksumbyte;
}


DATA Write an 8051 C program to perform the checksum operation to
CONVERSION ensure data integrity. If data is good, send ASCII character ‘G’ to P0.
Otherwise send ‘B’ to P0.

Checksum Byte Solution:

in ROM #include <reg51.h>
(cont’) void main(void)
{
unsigned char mydata[]
={0x25,0x62,0x3F,0x52,0xE8};
unsigned char shksum=0;
unsigned char x;
for (x=0;x<5;x++)
chksum=chksum+mydata[x];
if (chksum==0)
P0=‘G’;
else
P0=‘B’;
}


DATA Write an 8051 C program to convert 11111101 (FD hex) to decimal
CONVERSION and display the digits on P0, P1 and P2.
Solution:
Binary (hex) to #include <reg51.h>
Decimal and void main(void)
ASCII {
Conversion unsigned char x,binbyte,d1,d2,d3;
binbyte=0xFD;
x=binbyte/10;
d1=binbyte%10;
d2=x%10;
d3=x/10;
P0=d1;
P1=d2;
P2=d3;
}


The 8051 C compiler allocates RAM
ACCESSING
CODE ROM
locations
Bank 0 – addresses 0 – 7
RAM Data Individual variables – addresses 08 and
Space Usage beyond
by 8051 C Array elements – addresses right after
Compiler variables
Array elements need contiguous RAM locations
and that limits the size of the array due to the
fact that we have only 128 bytes of RAM for
everything
Stack – addresses right after array
elements


ACCESSING Compile and single-step the following program on your 8051
CODE ROM simulator. Examine the contents of the 128-byte RAM space to locate
the ASCII values.

RAM Data Solution:

Space Usage #include <reg51.h>
by 8051 C void main(void)
Compiler {
unsigned char mynum[]=“ABCDEF”; //RAM space
for (z=0;z<=6;z++)
P1=mynum[z];
}


ACCESSING Write, compile and single-step the following program on your 8051
CODE ROM simulator. Examine the contents of the code space to locate the values.
Solution:
RAM Data #include <reg51.h>
Space Usage void main(void)
by 8051 C {
Compiler unsigned char mydata[100]; //RAM space
unsigned char x,z=0;
(cont’) for (x=0;x<100;x++)
{
z--;
mydata[x]=z;
P1=z;
}
}


One of the new features of the 8052
ACCESSING
CODE ROM
was an extra 128 bytes of RAM space
The extra 128 bytes of RAM helps the
8052 RAM Data 8051/52 C compiler to manage its
Space registers and resources much more
effectively
We compile the C programs for the
8052 microcontroller
Use the reg52.h header file
Choose the8052 option when compiling
the program


ACCESSING Compile and single-step the following program on your 8051
CODE ROM simulator. Examine the contents of the code space to locate the ASCII
values.
(cont’) To make the C compiler use the
Solution: code space instead of the RAM
#include <reg51.h> space, we need to put the
keyword code in front of the
void main(void) variable declaration
{
code unsigned char mynum[]=“ABCDEF”;
unsigned char z;
for (z=0;z<=6;z++)
P1=mynum[z];
}


ACCESSING Compare and contrast the following programs and discuss the
CODE ROM advantages and disadvantages of each one.
(cont’) (a)
#include <reg51.h> Short and simple, but the
void main(void) individual characters are
{ embedded into the program and it
P1=‘H’; mixes the code and data together
P1=‘E’;
P1=‘L’;
P1=‘L’;
P1=‘O’;
}

...


...
ACCESSING Use the RAM data space to store
CODE ROM (b)
#include <reg51.h>
array elements, therefore the size
(cont’) void main(void) of the array is limited
{
unsigned char mydata[]=“HELLO”;
unsigned char z;
for (z=0;z<=5;z++)
P1=mydata[z]; Use a separate area of the
} code space for data. This
(c) allows the size of the array to
be as long as you want if you
#include <reg51.h>
void main(void) have the on-chip ROM.
{
code unsigned char mydata[]=“HELLO”;
unsigned char z;
for (z=0;z<=5;z++)
P1=mydata[z];
}
However, the more code space you use for data,
the less space is left for your program code


Serializing data is a way of sending a
DATA
SERIALIZATION
byte of data one bit at a time through
a single pin of microcontroller
Using the serial port (Chap. 10)
Transfer data one bit a time and control
the sequence of data and spaces in
between them
In many new generations of devices such as
LCD, ADC, and ROM the serial versions are
becoming popular since they take less space on
a PCB


DATA Write a C program to send out the value 44H serially one bit at a time
SERIALIZATION via P1.0. The LSB should go out first.
(cont’) Solution:
#include <reg51.h>
sbit P1b0=P1^0;
sbit regALSB=ACC^0;

void main(void)
{
unsigned char conbyte=0x44;
unsigned char x;
ACC=conbyte;
for (x=0;x<8;x++)
{
P1b0=regALSB;
ACC=ACC>>1;
}
}


DATA Write a C program to send out the value 44H serially one bit at a time
SERIALIZATION via P1.0. The MSB should go out first.
(cont’) Solution:
#include <reg51.h>
sbit P1b0=P1^0;
sbit regAMSB=ACC^7;

void main(void)
{
unsigned char conbyte=0x44;
unsigned char x;
ACC=conbyte;
for (x=0;x<8;x++)
{
P1b0=regAMSB;
ACC=ACC<<1;
}
}


DATA Write a C program to bring in a byte of data serially one bit at a time
SERIALIZATION via P1.0. The LSB should come in first.
(cont’) Solution:
#include <reg51.h>
sbit P1b0=P1^0;
sbit ACCMSB=ACC^7;
bit membit;

void main(void)
{
unsigned char x;
for (x=0;x<8;x++)
{
membit=P1b0;
ACC=ACC>>1;
ACCMSB=membit;
}
P2=ACC;
}


DATA Write a C program to bring in a byte of data serially one bit at a time
SERIALIZATION via P1.0. The MSB should come in first.
(cont’) Solution:
#include <reg51.h>
sbit P1b0=P1^0;
sbit regALSB=ACC^0;
bit membit;

void main(void)
{
unsigned char x;
for (x=0;x<8;x++)
{
membit=P1b0;
ACC=ACC<<1;
regALSB=membit;
}
P2=ACC;
}


HARDWARE CONNECTION
AND INTEL HEX FILE


Chung-Ping Young
楊中平


8051 family members (e.g, 8751,
PIN
DESCRIPTION
89C51, 89C52, DS89C4x0)
Have 40 pins dedicated for various
functions such as I/O, -RD, -WR, address,
data, and interrupts
Come in different packages, such as
DIP(dual in-line package),
QFP(quad flat package), and
LLC(leadless chip carrier)
Some companies provide a 20-pin version
of the 8051 with a reduced number of
I/O ports for less demanding applications


8051 pin diagram
PIN
DESCRIPTION P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
(cont’) P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
33 P0.6(AD6)
P1.7 8
8051/52 32 P0.7(AD7)
RST 9
(RXD)P3.0 10
(DS89C4x0 31 -EA/VPP
(TXD)P3.1 11 AT89C51 30 ALE/-PROG
(-INT0)P3.2 12 29 -PSEN
(-INT1)P3.3 13
8031) 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(-WR)P3.6 16 25 P2.4(A12)
(-RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


Provides +5V supply
PIN A total of 32 voltage to the chip
DESCRIPTION pins are set
aside for the
(cont’) four ports P0,
P1.0 1 40
39
Vcc
P1.1 2 P0.0(AD0)
P1, P2, P3, P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
where each port P1 P1.4 5 36 P0.3(AD3)
takes 8 pins P1.5 6 35 P0.4(AD4) P0
P1.6 7 34 P0.5(AD5)
33 P0.6(AD6)
P1.7 8 8051/52 32
RST 9 P0.7(AD7)
Vcc, GND, XTAL1, (RXD)P3.0 10
(DS89C4x0 31 -EA/VPP
XTAL2, RST, -EA (TXD)P3.1 11 AT89C51 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
are used by all (INT1)P3.3 13
8031) 28 P2.7(A15)
members of 8051 and P3 (T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
8031 families (WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11) P2
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
Grond GND 20 21 P2.0(A8)

-PSEN and ALE are used
mainly in 8031-baded systems


The 8051 has an on-chip oscillator but
PIN
DESCRIPTION
requires an external clock to run it
A quartz crystal oscillator is connected to
XTAL1 and inputs XTAL1 (pin19) and XTAL2 (pin18)
XTAL2 The quartz crystal oscillator also needs two
capacitors of 30 pF value

C2

XTAL2
P1.0 1 40 Vcc 30pF
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1) C1
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3) XTAL1
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
30pF
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP GND
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


If you use a frequency source other
PIN
DESCRIPTION
than a crystal oscillator, such as a TTL
oscillator
XTAL1 and It will be connected to XTAL1
XTAL2 XTAL2 is left unconnected
(cont’)
NC XTAL2

EXTERNAL
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0) OSCILLATOR XTAL1
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2) SIGNAL
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6) GND
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


The speed of 8051 refers to the
PIN
DESCRIPTION
maximum oscillator frequency
connected to XTAL
XTAL1 and ex. A 12-MHz chip must be connected to a
XTAL2 crystal with 12 MHz frequency or less
(cont’) We can observe the frequency on the
XTAL2 pin using the oscilloscope

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


RESET pin is an input and is active
PIN high (normally low)
DESCRIPTION
Upon applying a high pulse to this pin, the
microcontroller will reset and terminate all
RST activities
This is often referred to as a power-on reset
Activating a power-on reset will cause all values
in the registers to be lost
RESET value of some
Register Reset Value
P1.0 1 40 Vcc 8051 registers
P1.1
P1.2
2
3
39
38
P0.0(AD0)
P0.1(AD1) PC 0000
P1.3 4 37 P0.2(AD2)
P1.4
P1.5
5
6
36
35
P0.3(AD3)
P0.4(AD4)
we must place DPTR 0000
P1.6 7 34 P0.5(AD5)
P1.7
RST
8
9
33
32
P0.6(AD6)
P0.7(AD7)
the first line of ACC 00
8051 31 -EA/VPP
(RXD)P3.0
(TXD)P3.1
10
11(8031) 30
29
ALE/PROG
-PSEN
source code in PSW 00
(INT0)P3.2 12
P2.7(A15)
(INT1)P3.3 13 28
ROM location 0
SP 07
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2
XTAL1
18
19
23
22
P2.2(A10)
P2.1(A9) B 00
GND 20 21 P2.0(A8)
P0-P3 FF

In order for the RESET input to be
PIN
DESCRIPTION
effective, it must have a minimum
duration of 2 machine cycles
RST In other words, the high pulse must be
(cont’) high for a minimum of 2 machine cycles
before it is allowed to go low
Power-on RESET circuit Power-on RESET with debounce

Vcc Vcc
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0) 31 31
P1.2 3 38
37
P0.1(AD1)
EA/Vpp EA/Vpp
P1.3 4 P0.2(AD2)
36 P0.3(AD3)
P1.4 5 + 19
P1.5 6 35 P0.4(AD4) 10 uF 19 X1
P1.6 7 34 P0.5(AD5) X1 10 uF
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7) 30 pF 30 pF
8051 31
ALE/PROG
11.0592 MHz
(TXD)P3.1 11(8031) 30
(INT0)P3.2 12 29 -PSEN 8.2K
(INT1)P3.3 13 28 P2.7(A15) X2
(T0)P3.4 27 P2.6(A14) X2
(T1)P3.5
14
15 26 P2.5(A13) 30 pF 18 30 pF 18
(WR)P3.6 16 25 P2.4(A12) RST
(RD)P3.7 17 24 P2.3(A11) 9
XTAL2 18 23 P2.2(A10) RST
XTAL1 22 P2.1(A9)
19 9
GND 20 21 P2.0(A8) 8.2K


EA, “external access’’, is an input pin
PIN
DESCRIPTION
and must be connected to Vcc or GND
The 8051 family members all come with
EA on-chip ROM to store programs
-EA pin is connected to Vcc
The 8031 and 8032 family members do no
have on-chip ROM, so code is stored on

an external ROM and is fetched by
P1.0
P1.1
P1.2
1
2
3
40
39
38
Vcc
P0.0(AD0)
P0.1(AD1)
8031/32
-EA pin must be connected to GND to indicate
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)

that the code is stored externally
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


The following two pins are used mainly
PIN in 8031-based systems
DESCRIPTION
PSEN, “program store enable’’, is an
PSEN And ALE output pin
This pin is connected to the OE pin of the
ROM
ALE, “address latch enable”, is an
output pin and is active high
Port 0 provides both address and data
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
4 37 P0.2(AD2)
The 8031 multiplexes address and data through
P1.3
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)

port 0 to save pins
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
8051 31
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
10
11(8031) 30
12 29
-EA/VPP
ALE/PROG
-PSEN
ALE pin is used for demultiplexing the address
(INT1)P3.3
(T0)P3.4
13
14
28
27
P2.7(A15)
P2.6(A14) and data by connecting to the G pin of the
74LS373 chip
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


The four 8-bit I/O ports P0, P1, P2 and
PIN
DESCRIPTION
P3 each uses 8 pins
All the ports upon RESET are
I/O Port Pins configured as output, ready to be used
as input ports

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


Port 0 is also designated as AD0-AD7,
PIN
DESCRIPTION
allowing it to be used for both address
and data
Port 0 When connecting an 8051/31 to an
external memory, port 0 provides both
address and data
The 8051 multiplexes address and data
through port 0 to save pins
1 40 Vcc
ALE indicates if P0 has address or data
P1.0
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
5 36 P0.3(AD3)
When ALE=0, it provides data D0-D7
P1.4
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST
(RXD)P3.0
9
10
32
8051 31 P0.7(AD7)
-EA/VPP
ALE/PROG
When ALE=1, it has address A0-A7
(TXD)P3.1 11(8031) 30
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


It can be used for input or output,
PIN
DESCRIPTION
each pin must be connected externally
to a 10K ohm pull-up resistor
Port 0 This is due to the fact that P0 is an open
(cont’) drain, unlike P1, P2, and P3
Open drain is a term used for MOS chips in the
same way that open collector is used for TTL
chips
Vcc
P1.0
P1.1
1
2
40
39
Vcc
P0.0(AD0)
10 K
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3) P0.0
P1.5 6 35 P0.4(AD4) P0.1
P1.6 7 34 P0.5(AD5)

Port 0
P1.7 8 33
32
P0.6(AD6)
8051/52 P0.2
RST 9 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP P0.3
(TXD)P3.1 11(8031) 30 ALE/PROG P0.4
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3
(T0)P3.4
13 28
27
P2.7(A15)
P2.6(A14)
P0.5
14
(T1)P3.5 15 26 P2.5(A13)
P2.4(A12)
P0.6
(WR)P3.6 16 25
(RD)P3.7 17 24 P2.3(A11) P0.7
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


In 8051-based systems with no
PIN
DESCRIPTION
external memory connection
Both P1 and P2 are used as simple I/O
Port 1 and In 8031/51-based systems with
Port 2 external memory connections
Port 2 must be used along with P0 to
provide the 16-bit address for the external
P1.0 1 40 Vcc
memory
P1.1 2 39 P0.0(AD0)
P1.2
P1.3
3
4
38
37
36
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0 provides the lower 8 bits via A0 – A7
P1.4 5

P2 is used for the upper 8 bits of the 16-bit
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST
(RXD)P3.0
(TXD)P3.1
9
10
32
8051 31
11(8031) 30
P0.7(AD7)
-EA/VPP
ALE/PROG
address, designated as A8 – A15, and it cannot
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
12
13
14
29
28
27
-PSEN
P2.7(A15)
P2.6(A14)
be used for I/O
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


PIN
DESCRIPTION Port 3 does not need any pull-up resistors
Port 3 has the additional function of
Port 3 providing some extremely important
signals
P3 Bit Function Pin
Serial
P3.0 RxD 10 communications
P1.0 1 40 Vcc
P3.1 TxD 11
P1.1 2 39 P0.0(AD0) External
P1.2
P1.3
3
4
38
37
36
P0.1(AD1)
P0.2(AD2) P3.2 INT0 12 interrupts
P1.4 5 P0.3(AD3)
35 P0.4(AD4)
P3.3 INT1 13
P1.5 6
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
P3.4 T0 14 Timers
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
P3.5 T1 15
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12) Read/Write signals
(RD)P3.7
XTAL2
17
18
24
23
P2.3(A11)
P2.2(A10) P3.6 WR 16 of external memories
XTAL1 19 22 P2.1(A9)

P3.7 RD 17
GND 20 21 P2.0(A8)


Intel hex file is a widely used file
EXPLAINING
INTEL HEX
format
FILE Designed to standardize the loading of
executable machine codes into a ROM chip
Loaders that come with every ROM
burner (programmer) support the Intel
hex file format
In many newer Windows-based
assemblers the Intel hex file is produced
automatically (by selecting the right
setting)
In DOS-based PC you need a utility called
OH (object-to-hex) to produce that


In the DOS environment
EXPLAINING
INTEL HEX The object file is fed into the linker
FILE program to produce the abs file
(cont’) The abs file is used by systems that have a
monitor program
Then the abs file is fed into the OH utility
to create the Intel hex file
The hex file is used only by the loader of an

EPROM programmer to load it into the ROM
chip


The location is the address where the
LOC OBJ LINE opcodes (object codes) are placed

EXPLAINING 0000
0000 758055
1
2 MAIN:
ORG 0H
MOV P0,#55H
INTEL HEX 0003 759055 3 MOV P1,#55H
FILE 0006 75A055 4 MOV P2,#55H
0009 7DFA 5 MOV R5,#250
(cont’) 000B 111C 6 ACALL MSDELAY
000D 7580AA 7 MOV P0,#0AAH
0010 7590AA 8 MOV P1,#0AAH
0013 75A0AA 9 MOV P2,#0AAH
0016 7DFA 10 MOV R5,#250
0018 111C 11 ACALL MSDELAY
001A 80E4 12 SJMP MAIN
13 ;--- THE 250 MILLISECOND DELAY.
14 MSDELAY:
001C 7C23 15 HERE3: MOV R4,#35
001E 7B4F 16 HERE2: MOV R3,#79
0020 DBFE 17 HERE1: DJNZ R3,HERE1
0022 DCFA 18 DJNZ R4,HERE2
0024 DDF6 19 DJNZ R5,HERE3
0026 22 20 RET
21 END

The hex file provides the following:
EXPLAINING
INTEL HEX The number of bytes of information to be
FILE loaded
(cont’) The information itself
The starting address where the
information must be placed
:1000000075805575905575A0557DFA111C7580AA9F
:100010007590AA75A0AA7DFA111C80E47C237B4F01
:07002000DBFEDCFADDF62235
:00000001FF

:CC AAAA TT DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD SS
:10 0000 00 75805575905575A0557DFA111C7580AA 9F
:10 0010 00 7590AA75A0AA7DFA111C80E47C237B4F 01
:07 0020 00 DBFEDCFADDF622 35
:00 0000 01 FF


Each line starts with a colon Type –
00, there are more
EXPLAINING Count byte – how many bytes, lines to come after
INTEL HEX 00 to 16, are in the line this line
01, this is the last
FILE 16-bit address – The loader line and the
(cont’) places the first byte of data loading should
into this memory address stop after this line

:CC AAAA TT DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD SS
:10 0000 00 75805575905575A0557DFA111C7580AA 9F

:10 0010 00 7590AA75A0AA7DFA111C80E47C237B4F 01
:07 0020 00 DBFEDCFADDF622 35
:00 0000 01 FF

Real information (data or code) – There is a maximum
of 16 bytes in this part. The loader places this
information into successive memory locations of ROM

Single byte – this last byte is the checksum
byte of everything in that line


Example 8-4
EXPLAINING
INTEL HEX Verify the checksum byte for line 3 of Figure 8-9. Verify also that
the information is not corrupted.
FILE
Solution:
(cont’)
:07 0020 00 DBFEDCFADDF622
:07 0020 00 DBFEDCFADDF622 35
35

07+00+20+00+DB+FE+DC+FA+DD+F6+22=5CBH
Dropping the carry 5

CBH

2’s complement 35H

If we add all the information including the checksum byte, and drop
the carries, we get 00.

5CBH + 35H = 600H


TIMER PROGRAMMING


Chung-Ping Young
楊中平


The 8051 has two timers/counters,
PROGRAMMING
TIMERS they can be used either as
Timers to generate a time delay or as
Event counters to count events happening
outside the microcontroller
Both Timer 0 and Timer 1 are 16 bits
wide

Since 8051 has an 8-bit architecture, each
16-bits timer is accessed as two separate
registers of low byte and high byte


Accessed as low byte and high byte
PROGRAMMING
The low byte register is called TL0/TL1
TIMERS and
The high byte register is called TH0/TH1
Timer 0 & 1
Registers Accessed like any other register
MOV TL0,#4FH
MOV R5,TH0
TH0 TL0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TH1 TL1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0


Both timers 0 and 1 use the same
PROGRAMMING
TIMERS register, called TMOD (timer mode), to
set the various timer operation modes
TMOD TMOD is a 8-bit register
Register
The lower 4 bits are for Timer 0
The upper 4 bits are for Timer 1
In each case,

The lower 2 bits are used to set the timer mode
The upper 2 bits to specify the operation
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0

Timer1 Timer0


(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
PROGRAMMING
Timer1 Timer0
TIMERS

Operating Mode
TMOD M1 M0 Mode

0 0 0
Register 13-bit timer mode
8-bit timer/counter THx with TLx as 5-bit
(cont’) prescaler
0 1 1 16-bit timer mode
16-bit timer/counter THx and TLx are

cascaded; there is no prescaler

Gating control when set. 1 0 2 8-bit auto reload
8-bit auto reload timer/counter; THx holds a
Timer/counter is enable value which is to be reloaded TLx each time
only while the INTx pin is it overfolws
high and the TRx control 1 1 3 Split timer mode
pin is set
When cleared, the timer is Timer or counter selected
enabled whenever the TRx Cleared for timer operation (input from internal
control bit is set system clock)
Set for counter operation (input from Tx input pin)

Example 9-1
PROGRAMMING Indicate which mode and which timer are selected for each of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV TMOD, #12H
TIMERS
Solution:
We convert the value from hex to binary. From Figure 9-3 we have:
TMOD (a) TMOD = 00000001, mode 1 of timer 0 is selected.
Register (b) TMOD = 00100000, mode 2 of timer 1 is selected.
(c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer 1 are
(cont’) selected.

If C/T = 0, it is used
as a timer for time Example 9-2
delay generation. Find the timer’s clock frequency and its period for various 8051-based system,
The clock source for with the crystal frequency 11.0592 MHz when C/T bit of TMOD is 0.
the time delay is the
Solution:
crystal frequency of
XTAL
the 8051 ÷12
oscillator

1/12 × 11.0529 MHz = 921.6 MHz;
T = 1/921.6 kHz = 1.085 us


Timers of 8051 do starting and stopping
by either software or hardware control
PROGRAMMING
In using software to start and stop the timer
TIMERS where GATE=0
The start and stop of the timer are controlled by
TMOD way of software by the TR (timer start) bits TR0
Register and TR1
– The SETB instruction starts it, and it is
stopped by the CLR instruction
GATE
– These instructions start and stop the timers
as long as GATE=0 in the TMOD register
The hardware way of starting and stopping
the timer by an external source is achieved
• Timer 0, mode 2 by making GATE=1 in the TMOD register
• C/T = 0 to use
XTAL clock source Find the value for TMOD if we want to program timer 0 in mode 2,
• gate = 0 to use use 8051 XTAL for the clock source, and use instructions to start
internal (software) start and stop the timer.
and stop method.
TMOD = 0000 0010


The following are the characteristics
PROGRAMMING and operations of mode1:
TIMERS
1. It is a 16-bit timer; therefore, it allows
value of 0000 to FFFFH to be loaded into
Mode 1 the timer’s register TL and TH
Programming
2. After TH and TL are loaded with a 16-bit
initial value, the timer must be started
This is done by SETB TR0 for timer 0 and
SETB TR1 for timer 1
3. After the timer is started, it starts to
count up
It counts up until it reaches its limit of FFFFH

XTAL TH TL TF
÷12
oscillator
TF goes high Overflow
C/T = 0 TR when FFFF → 0 flag

3. (cont’)
When it rolls over from FFFFH to 0000, it sets
PROGRAMMING high a flag bit called TF (timer flag)
TIMERS – Each timer has its own timer flag: TF0 for
timer 0, and TF1 for timer 1
– This timer flag can be monitored
Mode 1 When this timer flag is raised, one option
Programming would be to stop the timer with the
(cont’) instructions CLR TR0 or CLR TR1, for timer 0
and timer 1, respectively
4. After the timer reaches its limit and rolls

over, in order to repeat the process
TH and TL must be reloaded with the original
value, and
TF must be reloaded to 0

XTAL TH TL TF
÷12
oscillator
TF goes high Overflow
C/T = 0 TR when FFFF → 0 flag

To generate a time delay
PROGRAMMING 1. Load the TMOD value register indicating
TIMERS which timer (timer 0 or timer 1) is to be
used and which timer mode (0 or 1) is
selected
Mode 1
Programming 2. Load registers TL and TH with initial count
value
Steps to Mode 1 3. Start the timer
Program 4. Keep monitoring the timer flag (TF) with
the JNB TFx,target instruction to see
if it is raised
Get out of the loop when TF becomes high
5. Stop the timer
6. Clear the TF flag for the next round
7. Go back to Step 2 to load TH and TL
again

Example 9-4
PROGRAMMING In the following program, we create a square wave of 50% duty cycle (with
equal portions high and low) on the P1.5 bit. Timer 0 is used to generate the
TIMERS time delay. Analyze the program

MOV TMOD,#01 ;Timer 0, mode 1(16-bit mode)
Mode 1 HERE: MOV TL0,#0F2H ;TL0=F2H, the low byte
Programming MOV TH0,#0FFH ;TH0=FFH, the high byte
CPL P1.5 ;toggle P1.5
ACALL DELAY
Steps to Mode 1 SJMP HERE
Program
(cont’) In the above program notice the following step.
1. TMOD is loaded.
2. FFF2H is loaded into TH0-TL0.
3. P1.5 is toggled for the high and low portions of the pulse.
…


Example 9-4 (cont’)

DELAY:
PROGRAMMING SETB TR0 ;start the timer 0
TIMERS AGAIN: JNB TF0,AGAIN ;monitor timer flag 0
;until it rolls over
CLR TR0 ;stop timer 0
CLR TF0 ;clear timer 0 flag
Mode 1 RET
Programming 4. The DELAY subroutine using the timer is called.
5. In the DELAY subroutine, timer 0 is started by the SETB TR0 instruction.
Steps to Mode 1 6. Timer 0 counts up with the passing of each clock, which is provided by the
crystal oscillator. As the timer counts up, it goes through the states of FFF3,
Program

FFF4, FFF5, FFF6, FFF7, FFF8, FFF9, FFFA, FFFB, and so on until it
(cont’) reaches FFFFH. One more clock rolls it to 0, raising the timer flag (TF0=1).
At that point, the JNB instruction falls through.

FFF2 FFF3 FFF4 FFFF 0000

TF=0 TF=0 TF=0 TF=0 TF=1
7. Timer 0 is stopped by the instruction CLR TR0. The DELAY subroutine
ends, and the process is repeated.
Notice that to repeat the process, we must reload the TL and TH registers, and
start the process is repeated …


Example 9-5
In Example 9-4, calculate the amount of time delay in the DELAY
PROGRAMMING subroutine generated by the timer. Assume XTAL = 11.0592 MHz.
TIMERS Solution:
The timer works with a clock frequency of 1/12 of the XTAL
Mode 1 frequency; therefore, we have 11.0592 MHz / 12 = 921.6 kHz as the
timer frequency. As a result, each clock has a period of T =
Programming 1/921.6kHz = 1.085us. In other words, Timer 0 counts up each 1.085
us resulting in delay = number of counts × 1.085us.
Steps to Mode 1 The number of counts for the roll over is FFFFH – FFF2H = 0DH (13
Program

decimal). However, we add one to 13 because of the extra clock
(cont’) needed when it rolls over from FFFF to 0 and raise the TF flag. This
gives 14 × 1.085us = 15.19us for half the pulse. For the entire period it
is T = 2 × 15.19us = 30.38us as the time delay generated by the timer.

(a) in hex (b) in decimal
(FFFF – YYXX + 1) × Convert YYXX values
1.085 us, where YYXX of the TH, TL register
are TH, TL initial to decimal to get a
values respectively. NNNNN decimal, then
Notice that value (65536 - NNNN) ×
YYXX are in hex. 1.085 us


Example 9-6
In Example 9-5, calculate the frequency of the square wave generated
on pin P1.5.
PROGRAMMING
TIMERS Solution:
In the timer delay calculation of Example 9-5, we did not include the
overhead due to instruction in the loop. To get a more accurate timing,
Mode 1 we need to add clock cycles due to this instructions in the loop. To do
Programming that, we use the machine cycle from Table A-1 in Appendix A, as
shown below.
Cycles
Steps to Mode 1 HERE: MOV TL0,#0F2H 2
Program MOV TH0,#0FFH 2
(cont’) CPL P1.5 1
ACALL DELAY 2
SJMP HERE 2
DELAY:
SETB TR0 1
AGAIN: JNB TF0,AGAIN 14
CLR TR0 1
CLR TF0 1
RET 2
Total 28
T = 2 × 28 × 1.085 us = 60.76 us and F = 16458.2 Hz

Example 9-7
Find the delay generated by timer 0 in the following code, using both
PROGRAMMING of the Methods of Figure 9-4. Do not include the overhead due to
TIMERS instruction.
CLR P2.3 ;Clear P2.3
Mode 1 MOV TMOD,#01 ;Timer 0, 16-bitmode
HERE: MOV TL0,#3EH ;TL0=3Eh, the low byte
Programming MOV TH0,#0B8H ;TH0=B8H, the high byte
SETB P2.3 ;SET high timer 0
SETB TR0 ;Start the timer 0
Steps to Mode 1 AGAIN: JNB TF0,AGAIN ;Monitor timer flag 0
Program CLR TR0 ;Stop the timer 0
(cont’) CLR TF0
CLR P2.3
;Clear TF0 for next round

Solution:
(a) (FFFFH – B83E + 1) = 47C2H = 18370 in decimal and 18370 ×
1.085 us = 19.93145 ms
(b) Since TH – TL = B83EH = 47166 (in decimal) we have 65536 –
47166 = 18370. This means that the timer counts from B38EH to
FFFF. This plus Rolling over to 0 goes through a total of 18370 clock
cycles, where each clock is 1.085 us in duration. Therefore, we have
18370 × 1.085 us = 19.93145 ms as the width of the pulse.

Example 9-8
Modify TL and TH in Example 9-7 to get the largest time delay
PROGRAMMING possible. Find the delay in ms. In your calculation, exclude the
TIMERS overhead due to the instructions in the loop.
Solution:
To get the largest delay we make TL and TH both 0. This will count
Mode 1 up from 0000 to FFFFH and then roll over to zero.
Programming CLR P2.3 ;Clear P2.3
MOV TMOD,#01 ;Timer 0, 16-bitmode
Steps to Mode 1 HERE: MOV TL0,#0 ;TL0=0, the low byte
MOV TH0,#0 ;TH0=0, the high byte
Program

SETB P2.3 ;SET high P2.3
(cont’) SETB TR0 ;Start timer 0
AGAIN: JNB TF0,AGAIN ;Monitor timer flag 0
CLR TR0 ;Stop the timer 0
CLR TF0 ;Clear timer 0 flag
CLR P2.3
Making TH and TL both zero means that the timer will count from
0000 to FFFF, and then roll over to raise the TF flag. As a result, it
goes through a total Of 65536 states. Therefore, we have delay =
(65536 - 0) × 1.085 us = 71.1065ms.


Example 9-9
The following program generates a square wave on P1.5 continuously
PROGRAMMING using timer 1 for a time delay. Find the frequency of the square
TIMERS wave if XTAL = 11.0592 MHz. In your calculation do not
include the overhead due to Instructions in the loop.

Mode 1 MOV
AGAIN: MOV
TMOD,#10;Timer 1, mod 1 (16-bitmode)
TL1,#34H ;TL1=34H, low byte of timer
Programming MOV TH1,#76H ;TH1=76H, high byte timer
SETB TR1 ;start the timer 1
BACK: JNB TF1,BACK ;till timer rolls over
Steps to Mode 1 CLR TR1 ;stop the timer 1
Program CPL P1.5 ;comp. p1. to get hi, lo
(cont’) CLR TF1 ;clear timer flag 1
SJMP AGAIN ;is not auto-reload
Solution:
Since FFFFH – 7634H = 89CBH + 1 = 89CCH and 89CCH = 35276
clock count and 35276 × 1.085 us = 38.274 ms for half of the
square wave. The frequency = 13.064Hz.
Also notice that the high portion and low portion of the square wave
pulse are equal. In the above calculation, the overhead due to all
the instruction in the loop is not included.


To calculate the values to be loaded
PROGRAMMING
TIMERS into the TL and TH registers, look at
the following example
Mode 1 Assume XTAL = 11.0592 MHz, we can
Programming use the following steps for finding the TH,
TL registers’ values
Finding the 1. Divide the desired time delay by 1.085 us
Loaded Timer
2. Perform 65536 – n, where n is the decimal
Values
value we got in Step1
3. Convert the result of Step2 to hex, where
yyxx is the initial hex value to be loaded into
the timer’s register
4. Set TL = xx and TH = yy


Example 9-10
Assume that XTAL = 11.0592 MHz. What value do we need to load
PROGRAMMING the timer’s register if we want to have a time delay of 5 ms
TIMERS (milliseconds)? Show the program for timer 0 to create a pulse width
of 5 ms on P2.3.

Mode 1 Solution:
Since XTAL = 11.0592 MHz, the counter counts up every 1.085 us.
Programming This means that out of many 1.085 us intervals we must make a 5 ms
pulse. To get that, we divide one by the other. We need 5 ms / 1.085
Finding the us = 4608 clocks. To Achieve that we need to load into TL and TH
Loaded Timer the value 65536 – 4608 = EE00H. Therefore, we have TH = EE and
TL = 00.
Values
(cont’) CLR P2.3 ;Clear P2.3
MOV TMOD,#01 ;Timer 0, 16-bitmode
HERE: MOV TL0,#0 ;TL0=0, the low byte
MOV TH0,#0EEH ;TH0=EE, the high byte
SETB P2.3 ;SET high P2.3
SETB TR0 ;Start timer 0
AGAIN: JNB TF0,AGAIN ;Monitor timer flag 0


Example 9-11
PROGRAMMING Assume that XTAL = 11.0592 MHz, write a program to generate a
square wave of 2 kHz frequency on pin P1.5.
TIMERS
Solution:
Mode 1 This is similar to Example 9-10, except that we must toggle the bit to
generate the square wave. Look at the following steps.
Programming (a) T = 1 / f = 1 / 2 kHz = 500 us the period of square wave.
(b) 1 / 2 of it for the high and low portion of the pulse is 250 us.
Finding the (c) 250 us / 1.085 us = 230 and 65536 – 230 = 65306 which in hex
Loaded Timer is FF1AH.
Values (d) TL = 1A and TH = FF, all in hex. The program is as follow.
(cont’) MOV TMOD,#01 ;Timer 0, 16-bitmode
AGAIN: MOV TL1,#1AH ;TL1=1A, low byte of timer
MOV TH1,#0FFH ;TH1=FF, the high byte
BACK: JNB TF1,BACK ;until timer rolls over
CLR P1.5 ;Clear timer flag 1
SJMP AGAIN ;Reload timer


Example 9-12
Assume XTAL = 11.0592 MHz, write a program to generate a square
PROGRAMMING wave of 50 kHz frequency on pin P2.3.
TIMERS
Solution:
Look at the following steps.
Mode 1 (a) T = 1 / 50 = 20 ms, the period of square wave.
Programming (b) 1 / 2 of it for the high and low portion of the pulse is 10 ms.
(c) 10 ms / 1.085 us = 9216 and 65536 – 9216 = 56320 in decimal,
and in hex it is DC00H.
Finding the (d) TL = 00 and TH = DC (hex).
Loaded Timer
Values MOV TMOD,#10H ;Timer 1, mod 1
(cont’) AGAIN: MOV TL1,#00 ;TL1=00,low byte of timer
MOV TH1,#0DCH ;TH1=DC, the high byte
CLR P2.3 ;Comp. p2.3 to get hi, lo
SJMP AGAIN ;Reload timer
;mode 1 isn’t auto-reload


Example 9-13
PROGRAMMING Examine the following program and find the time delay in seconds.
TIMERS Exclude the overhead due to the instructions in the loop.

MOV TMOD,#10H ;Timer 1, mod 1
Mode 1 MOV R3,#200 ;cnter for multiple delay
Programming AGAIN: MOV TL1,#08H ;TL1=08,low byte of timer
MOV TH1,#01H ;TH1=01,high byte
Generating Large
Time Delay
CLR TF1 ;clear Timer 1 flag
DJNZ R3,AGAIN ;if R3 not zero then
;reload timer
Solution:
TH-TL = 0108H = 264 in decimal and 65536 – 264 = 65272. Now
65272 × 1.085 μs = 70.820 ms, and for 200 of them we have
200 ×70.820 ms = 14.164024 seconds.


The following are the characteristics
PROGRAMMING and operations of mode 2:
TIMERS
1. It is an 8-bit timer; therefore, it allows
only values of 00 to FFH to be loaded
Mode 2 into the timer’s register TH
Programming
2. After TH is loaded with the 8-bit value,
the 8051 gives a copy of it to TL
Then the timer must be started
This is done by the instruction SETB TR0 for
timer 0 and SETB TR1 for timer 1
3. After the timer is started, it starts to
count up by incrementing the TL register
It counts up until it reaches its limit of FFH
When it rolls over from FFH to 00, it sets high
the TF (timer flag)


4. When the TL register rolls from FFH to 0
PROGRAMMING and TF is set to 1, TL is reloaded
TIMERS automatically with the original value kept
by the TH register
Mode 2 To repeat the process, we must simply clear
Programming TF and let it go without any need by the
(cont’) programmer to reload the original value
This makes mode 2 an auto-reload, in
contrast with mode 1 in which the
programmer has to reload TH and TL

XTAL Overflow
÷12 TL TF
oscillator flag
TR Reload TF goes high
C/T = 0
when FF → 0
TH


To generate a time delay
PROGRAMMING
1. Load the TMOD value register indicating
TIMERS which timer (timer 0 or timer 1) is to be
used, and the timer mode (mode 2) is
Mode 2 selected
Programming 2. Load the TH registers with the initial
count value
Steps to Mode 2
Program 3. Start timer
4. Keep monitoring the timer flag (TF) with
the JNB TFx,target instruction to see
whether it is raised
Get out of the loop when TF goes high
5. Clear the TF flag
6. Go back to Step4, since mode 2 is auto-
reload


Example 9-14
PROGRAMMING Assume XTAL = 11.0592 MHz, find the frequency of the square
TIMERS wave generated on pin P1.0 in the following program
MOV TMOD,#20H ;T1/8-bit/auto reload
Mode 2 MOV TH1,#5 ;TH1 = 5
Programming BACK:
SETB
JNB
TR1
TF1,BACK
;start the timer 1
;till timer rolls over
CPL P1.0 ;P1.0 to hi, lo
Steps to Mode 2 CLR TF1 ;clear Timer 1 flag
Program SJMP BACK ;mode 2 is auto-reload
(cont’)
Solution:
First notice the target address of SJMP. In mode 2 we do not need to
reload TH since it is auto-reload. Now (256 - 05) × 1.085 us =
251 × 1.085 us = 272.33 us is the high portion of the pulse. Since
it is a 50% duty cycle square wave, the period T is twice that; as
a result T = 2 × 272.33 us = 544.67 us and the frequency =
1.83597 kHz


Example 9-15
PROGRAMMING Find the frequency of a square wave generated on pin P1.0.
TIMERS
Solution:

Mode 2 MOV TMOD,#2H ;Timer 0, mod 2
;(8-bit, auto reload)
Programming MOV TH0,#0
AGAIN: MOV R5,#250 ;multiple delay count
Steps to Mode 2 ACALL DELAY
Program CPL P1.0
(cont’) SJMP AGAIN

DELAY: SETB TR0 ;start the timer 0
BACK: JNB TF0,BACK ;stay timer rolls over
CLR TR0 ;stop timer
CLR TF0 ;clear TF for next round
DJNZ R5,DELAY
RET
T = 2 ( 250 × 256 × 1.085 us ) = 138.88ms, and frequency = 72 Hz


Example 9-16
PROGRAMMING Assuming that we are programming the timers for mode 2, find the
value (in hex) loaded into TH for each of the following cases.
TIMERS
(a) MOV TH1,#-200 (b) MOV TH0,#-60
Mode 2 (c) MOV TH1,#-3 (d) MOV TH1,#-12
(e) MOV TH0,#-48
Programming
Solution:
Steps to Mode 2 You can use the Windows scientific calculator to verify the result
Program provided by the assembler. In Windows calculator, select
(cont’) decimal and enter 200. Then select hex, then +/- to get the TH
value. Remember that we only use the right two digits and ignore
the rest since our data is an 8-bit data.
Decimal 2’s complement (TH value)
-3 FDH
-12 F4H The advantage of using
The number 200 is the
-48 D0H negative values is that you
timer count till the TF
-60 C4H don’t need to calculate the
is set to 1
-200 38H value loaded to THx


Timers can also be used as counters
COUNTER
PROGRAMMING
counting events happening outside the
8051
When it is used as a counter, it is a pulse
outside of the 8051 that increments the
TH, TL registers
TMOD and TH, TL registers are the same
as for the timer discussed previously
Programming the timer in the last
section also applies to programming it
as a counter
Except the source of the frequency


The C/T bit in the TMOD registers
COUNTER
PROGRAMMING
decides the source of the clock for the
timer
C/T Bit in When C/T = 1, the timer is used as a
TMOD Register counter and gets its pulses from outside
the 8051
The counter counts up as pulses are fed from
pins 14 and 15, these pins are called T0 (timer
0 input) and T1 (timer 1 input)

Port 3 pins used for Timers 0 and 1

Pin Port Pin Function Description
14 P3.4 T0 Timer/counter 0 external input
15 P3.5 T1 Timer/counter 1 external input


Example 9-18
Assuming that clock pulses are fed into pin T1, write a program
COUNTER for counter 1 in mode 2 to count the pulses and display the state
PROGRAMMING of the TL1 count on P2, which connects to 8 LEDs.

Solution:
C/T Bit in MOV TM0D,#01100000B ;counter 1, mode 2,
;C/T=1 external pulses
TMOD Register MOV TH1,#0 ;clear TH1
(cont’) SETB P3.5 ;make T1 input
AGAIN: SETB TR1 ;start the counter
BACK: MOV A,TL1 ;get copy of TL
MOV P2,A ;display it on port 2
JNB TF1,Back ;keep doing, if TF = 0
CLR TR1 ;stop the counter 1
CLR TF1 ;make TF=0
SJMP AGAIN ;keep doing it
Notice in the above program the role of the instruction SETB P3.5.
Since ports are set up for output when the 8051 is powered up,
we make P3.5 an input port by making it high. In other words,
we must configure (set high) the T1 pin (pin P3.5) to allow
pulses to be fed into it.


COUNTER Timer with external input (Mode 1)
PROGRAMMING Timer Overflow
external flag
input pin
C/T Bit in
TH TL TF
3.4 or 3.5
TF goes high
TMOD Register C/T = 1 TR when FFFF → 0
(cont’)

Timer with external input (Mode 2)
Timer Overflow
external flag
input pin
3.4 or 3.5 TL TF

C/T = 1
TR Reload TF goes high
when FF → 0
TH


TCON (timer control) register is an 8-
COUNTER
PROGRAMMING
bit register
TCON: Timer/Counter Control Register
TCON
Register TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

The upper four
bits are used to The lower 4 bits
store the TF and are set aside for
TR bits of both controlling the
timer 0 and 1 interrupt bits


TCON register is a bit-addressable
COUNTER
PROGRAMMING
register
Equivalent instruction for the Timer Control Register
TCON For timer 0
Register SETB TR0 = SETB TCON.4
(cont’) CLR TR0 = CLR TCON.4
SETB TF0 = SETB TCON.5
CLR TF0 = CLR TCON.5
For timer 1
SETB TR1 = SETB TCON.6
CLR TR1 = CLR TCON.6
SETB TF1 = SETB TCON.7
CLR TF1 = CLR TCON.7


If GATE = 1, the start and stop of the
COUNTER
PROGRAMMING
timer are done externally through pins
P3.2 and P3.3 for timers 0 and 1,
TCON respectively
Register This hardware way allows to start or stop
the timer externally at any time via a
Case of GATE = 1
simple switch
XTAL
÷12 C/T = 0
oscillator

Tx Pin
Pin 3.4 or 3.5 C/T = 1

Gate TR
INT0 Pin
Pin 3.2 or 3.3


Example 9-20
Write an 8051 C program to toggle all the bits of port P1 continuously
PROGRAMMING with some delay in between. Use Timer 0, 16-bit mode to
TIMERS IN C generate the delay.

Solution:
Accessing #include <reg51.h>
void T0Delay(void);
Timer Registers void main(void){
while (1) {
P1=0x55;
T0Delay();
P1=0xAA;
T0Delay();
}
}
void T0Delay(){
TMOD=0x01; FFFFH – 3500H = CAFFH
TL0=0x00;
TH0=0x35; = 51967 + 1 = 51968
TR0=1; 51968 × 1.085 μs = 56.384 ms is the
while (TF0==0);
TR0=0; approximate delay
TF0=0;
}


To speed up the 8051, many recent
PROGRAMMING
TIMERS IN C
versions of the 8051 have reduced the
number of clocks per machine cycle
Calculating from 12 to four, or even one
Delay Length The frequency for the timer is always
Using Timers
1/12th the frequency of the crystal
attached to the 8051, regardless of the
8051 version


Example 9-21
Write an 8051 C program to toggle only bit P1.5 continuously every
PROGRAMMING 50 ms. Use Timer 0, mode 1 (16-bit) to create the delay. Test the
TIMERS IN C program on the (a) AT89C51 and (b) DS89C420.

Solution:
Times 0/1 #include <reg51.h>
void T0M1Delay(void);
Delay Using sbit mybit=P1^5;
void main(void){
Mode 1 (16-bit while (1) {
Non Auto- mybit=~mybit;
T0M1Delay();
reload) }
}
void T0M1Delay(void){
TMOD=0x01;
TL0=0xFD; FFFFH – 4BFDH = B402H
TH0=0x4B; = 46082 + 1 = 46083
TR0=1;
while (TF0==0); 46083 × 1.085 μs = 50 ms
TR0=0;
TF0=0;
}


Example 9-22
Write an 8051 C program to toggle all bits of P2 continuously every
PROGRAMMING 500 ms. Use Timer 1, mode 1 to create the delay.

TIMERS IN C Solution:
//tested for DS89C420, XTAL = 11.0592 MHz
#include <reg51.h>
Times 0/1 void T1M1Delay(void);
Delay Using
void main(void){
unsigned char x;
Mode 1 (16-bit P2=0x55;
while (1) {
Non Auto- P2=~P2;
reload)
for (x=0;x<20;x++)
T1M1Delay();
(cont’) }
}
TMOD=0x10;
TL1=0xFE; A5FEH = 42494 in decimal
TH1=0xA5; 65536 – 42494 = 23042
TR1=1;
while (TF1==0); 23042 × 1.085 μs = 25 ms and
TR1=0; 20 × 25 ms = 500 ms
TF1=0;
}

Example 9-25
PROGRAMMING A switch is connected to pin P1.2. Write an 8051 C program to
TIMERS IN C monitor SW and create the following frequencies on pin P1.7:
SW=0: 500Hz
SW=1: 750Hz, use Timer 0, mode 1 for both of them.
Times 0/1
Solution:
Delay Using #include <reg51.h>
Mode 1 (16-bit sbit mybit=P1^5;
sbit SW=P1^7;
Non Auto- void T0M1Delay(unsigned char);
void main(void){
reload) SW=1;
(cont’) while (1) {
mybit=~mybit;
if (SW==0)
T0M1Delay(0);
else
T0M1Delay(1);
}
}
.....


Example 9-25
PROGRAMMING
TIMERS IN C .....
void T0M1Delay(unsigned char c){
TMOD=0x01;
Times 0/1 if (c==0) {
Delay Using TL0=0x67;
TH0=0xFC;
FC67H = 64615
65536 – 64615 = 921
Mode 1 (16-bit }
else { 921 × 1.085 μs = 999.285 μs
Non Auto- TL0=0x9A; 1 / (999.285 μs × 2) = 500 Hz
reload) }
TH0=0xFD;
(cont’) TR0=1;
while (TF0==0);
TR0=0;
TF0=0;
}


Example 9-23
Write an 8051 C program to toggle only pin P1.5 continuously every
PROGRAMMING 250 ms. Use Timer 0, mode 2 (8-bit auto-reload) to create the
delay.
TIMERS IN C
Solution:
#include <reg51.h>
Times 0/1 void T0M2Delay(void);
Delay Using
sbit mybit=P1^5;
void main(void){ Due to overhead of the for loop
Mode 2 (8-bit unsigned char x,y;
while (1) {
in C, we put 36 instead of 40
Auto-reload) mybit=~mybit;
for (x=0;x<250;x++)
for (y=0;y<36;y++) //we put 36, not 40
T0M2Delay();
}
}
TMOD=0x02;
TH0=-23; 256 – 23 = 233
TR0=1; 23 × 1.085 μs = 25 μs and
while (TF0==0);
TR0=0; 25 μs × 250 × 40 = 250 ms
TF0=0;
}

Example 9-24
PROGRAMMING Write an 8051 C program to create a frequency of 2500 Hz on pin
TIMERS IN C P2.7. Use Timer 1, mode 2 to create delay.

Solution:
Times 0/1 #include <reg51.h>
void T1M2Delay(void);
Delay Using sbit mybit=P2^7;
Mode 2 (8-bit void main(void){
unsigned char x;
Auto-reload) while (1) {
mybit=~mybit;
(cont’) T1M2Delay();
}
}
TMOD=0x20; 1/2500 Hz = 400 μs
TH1=-184;
TR1=1; 400 μs /2 = 200 μs
while (TF1==0); 200 μs / 1.085 μs = 184
TR1=0;
TF1=0;
}


Example 9-26
PROGRAMMING Assume that a 1-Hz external clock is being fed into pin T1 (P3.5).
TIMERS IN C Write a C program for counter 1 in mode 2 (8-bit auto reload) to count
up and display the state of the TL1 count on P1. Start the count at 0H.

C Programming Solution:
#include <reg51.h>
of Timers as sbit T1=P3^5;
Counters void main(void){
T1=1;
TMOD=0x60;
TH1=0;
while (1) {
do {
TR1=1;
P1=TL1;
}
while (TF1==0);
TR1=0;
TF1=0;
}
}


Example 9-27
Assume that a 1-Hz external clock is being fed into pin T0 (P3.4).
PROGRAMMING Write a C program for counter 0 in mode 1 (16-bit) to count the pulses
TIMERS IN C and display the state of the TH0 and TL0 registers on P2 and P1,
respectively.

C Programming Solution:
#include <reg51.h>
of Timers as void main(void){
Counters T0=1;
TMOD=0x05;
(cont’) TL0=0
TH0=0;
while (1) {
do {
TR0=1;
P1=TL0;
P2=TH0;
}
while (TF0==0);
TR0=0;
TF0=0;
}
}


SERIAL COMMUNICATION

Chung-Ping Young
楊中平

National Cheng Kung University

Computers transfer data in two ways:
BASICS OF
SERIAL Parallel
COMMUNICA- Often 8 or more lines (wire conductors) are
used to transfer data to a device that is only a
TION few feet away
Serial
To transfer to a device located many meters
away, the serial method is used

The data is sent one bit at a time

Serial Transfer Parallel Transfer
D0

Sender Receiver Sender Receiver

D7

HANEL National Cheng Kung University 2

At the transmitting end, the byte of
BASICS OF data must be converted to serial bits
SERIAL using parallel-in-serial-out shift register
COMMUNICA-
TION At the receiving end, there is a serial-
(cont’) in-parallel-out shift register to receive
the serial data and pack them into byte
When the distance is short, the digital
signal can be transferred as it is on a
simple wire and requires no modulation
If data is to be transferred on the
telephone line, it must be converted
from 0s and 1s to audio tones
This conversion is performed by a device
called a modem, “Modulator/demodulator”

Serial data communication uses two
BASICS OF methods
SERIAL
Synchronous method transfers a block of
COMMUNICA- data at a time
TION
(cont’)
Asynchronous method transfers a single
byte at a time
It is possible to write software to use
either of these methods, but the

programs can be tedious and long
There are special IC chips made by many
manufacturers for serial communications
UART (universal asynchronous Receiver-
transmitter)
USART (universal synchronous-asynchronous
Receiver-transmitter)


If data can be transmitted and received,
BASICS OF it is a duplex transmission
SERIAL If data transmitted one way a time, it is
COMMUNICA- referred to as half duplex
TION If data can go both ways at a time, it is full
duplex
Half- and Full- This is contrast to simplex transmission
Duplex
Transmission Simplex Transmitter Receiver

Transmitter Receiver
Half Duplex
Receiver Transmitter

Transmitter Receiver
Full Duplex
Receiver Transmitter


A protocol is a set of rules agreed by
BASICS OF both the sender and receiver on
SERIAL How the data is packed
COMMUNICA- How many bits constitute a character
TION When the data begins and ends
Asynchronous serial data
Start and Stop communication is widely used for
Bits character-oriented transmissions

Each character is placed in between start
and stop bits, this is called framing
Block-oriented data transfers use the
synchronous method
The start bit is always one bit, but the
stop bit can be one or two bits


The start bit is always a 0 (low) and the
BASICS OF stop bit(s) is 1 (high)
SERIAL
COMMUNICA- ASCII character “A” (8-bit binary 0100 0001)
TION

Start and Stop
Start Mark
Bits Space Stop 0 1 0 0 0 0 0 1 Bit
Bit

(cont’)
D7 D0

Goes out last Goes out first
The 0 (low) is
referred to as space The transmission begins with a
start bit followed by D0, the
LSB, then the rest of the bits When there is no
until MSB (D7), and finally, transfer, the signal
the one stop bit indicating the is 1 (high), which is
end of the character referred to as mark


Due to the extended ASCII characters,
BASICS OF 8-bit ASCII data is common
SERIAL In older systems, ASCII characters were 7-
COMMUNICA- bit
TION In modern PCs the use of one stop bit
is standard
Start and Stop In older systems, due to the slowness of
Bits the receiving mechanical device, two stop
(cont’) bits were used to give the device sufficient
time to organize itself before transmission
of the next byte


Assuming that we are transferring a
BASICS OF text file of ASCII characters using 1
SERIAL stop bit, we have a total of 10 bits for
COMMUNICA- each character
TION This gives 25% overhead, i.e. each 8-bit
character with an extra 2 bits
Start and Stop In some systems in order to maintain
Bits data integrity, the parity bit of the
character byte is included in the data

(cont’)
frame
UART chips allow programming of the
parity bit for odd-, even-, and no-parity
options


The rate of data transfer in serial data
BASICS OF communication is stated in bps (bits per
SERIAL second)
COMMUNICA- Another widely used terminology for
TION bps is baud rate
It is modem terminology and is defined as
Data Transfer the number of signal changes per second
Rate In modems, there are occasions when a
single change of signal transfers several
bits of data
As far as the conductor wire is
concerned, the baud rate and bps are
the same, and we use the terms
interchangeably


The data transfer rate of given
BASICS OF computer system depends on
SERIAL communication ports incorporated into
COMMUNICA- that system
TION IBM PC/XT could transfer data at the rate
of 100 to 9600 bps
Data Transfer Pentium-based PCs transfer data at rates as
Rate high as 56K bps
(cont’) In asynchronous serial data communication,
the baud rate is limited to 100K bps


An interfacing standard RS232 was set
BASICS OF by the Electronics Industries Association
SERIAL (EIA) in 1960
COMMUNICA- The standard was set long before the
TION advent of the TTL logic family, its input
and output voltage levels are not TTL
RS232 compatible
Standards In RS232, a 1 is represented by -3 ~ -25 V,
while a 0 bit is +3 ~ +25 V, making -3 to
+3 undefined


RS232 DB-25 Pins
Pin Description Pin Description
BASICS OF 1 Protective ground 14 Secondary transmitted data

SERIAL 2 Transmitted data (TxD) 15 Transmitted signal element timing
3 Received data (RxD) 16 Secondary receive data
COMMUNICA- 4 Request to send (-RTS) 17 Receive signal element timing
TION 5 Clear to send (-CTS) 18 Unassigned
6 Data set ready (-DSR) 19 Secondary receive data
7 Signal ground (GND) 20 Data terminal ready (-DTR)
RS232 8 Data carrier detect (-DCD) 21 Signal quality detector
Standards 9/10 Reserved for data testing 22 Ring indicator (RI)

(cont’) 11 Unassigned 23 Data signal rate select
12 Secondary data carrier detect 24 Transmit signal element timing
13 Secondary clear to send 25 Unassigned

RS232 Connector DB-25


Since not all pins are used in PC cables,
BASICS OF IBM introduced the DB-9 version of the
SERIAL serial I/O standard
COMMUNICA-
TION RS232 Connector DB-9 RS232 DB-9 Pins
Pin Description
RS232 1 Data carrier detect (-DCD)

Standards 2 Received data (RxD)
3 Transmitted data (TxD)

(cont’)
4 Data terminal ready (DTR)
5 Signal ground (GND)
6 Data set ready (-DSR)
7 Request to send (-RTS)
8 Clear to send (-CTS)
9 Ring indicator (RI)


Current terminology classifies data
BASICS OF communication equipment as
SERIAL DTE (data terminal equipment) refers to
COMMUNICA- terminal and computers that send and
TION receive data
DCE (data communication equipment)
Data refers to communication equipment, such
as modems
Communication
Classification
The simplest connection between a PC
and microcontroller requires a minimum
of three pins, TxD, RxD, and ground
Null modem connection
DTE DTE
TxD TxD
RxD RxD

ground

DTR (data terminal ready)
BASICS OF When terminal is turned on, it sends out
SERIAL signal DTR to indicate that it is ready for
COMMUNICA- communication
TION DSR (data set ready)
When DCE is turned on and has gone
RS232 Pins through the self-test, it assert DSR to
indicate that it is ready to communicate
RTS (request to send)
When the DTE device has byte to transmit,
it assert RTS to signal the modem that it
has a byte of data to transmit
CTS (clear to send)
When the modem has room for storing the
data it is to receive, it sends out signal CTS
to DTE to indicate that it can receive the
data now

DCD (data carrier detect)
BASICS OF The modem asserts signal DCD to inform
SERIAL the DTE that a valid carrier has been
COMMUNICA- detected and that contact between it and
TION the other modem is established
RI (ring indicator)
RS232 Pins An output from the modem and an input to
(cont’) a PC indicates that the telephone is ringing
It goes on and off in synchronous with the
ringing sound


A line driver such as the MAX232 chip is
8051 required to convert RS232 voltage
CONNECTION levels to TTL levels, and vice versa
TO RS232 8051 has two pins that are used
specifically for transferring and
receiving data serially
These two pins are called TxD and RxD and
are part of the port 3 group (P3.0 and P3.1)
These pins are TTL compatible; therefore,
they require a line driver to make them
RS232 compatible


We need a line driver (voltage
8051 converter) to convert the R232’s signals
CONNECTION to TTL voltage levels that will be
TO RS232 acceptable to 8051’s TxD and RxD pins

MAX232 Vcc
C3
+
MAX232 requires
16 2 four capacitors
+
1 MAX232
C1
3 6 8051
4 C4
+
C2
+
MAX232
5 P3.1 11 11
TxD 14 2 5

T1in T1out
11 14
13 3
R1out R1in P3.0 10 12
12 13
RxD
T2in T2out
10 7
R2out R2int
DB-9
9 8

TTL side RS232 side
MAX232 has two
15
sets of line drivers


To save board space, some designers
8051 use MAX233 chip from Maxim
CONNECTION MAX233 performs the same job as MAX232
TO RS232 but eliminates the need for capacitors
Notice that MAX233 and MAX232 are not
MAX233 pin compatible
Vcc
13
7

14 MAX233 11

12
15
8051
16
17 MAX233
10 P3.1 11 2
TxD 5 2 5

T1in T1out
2 5
4 3
R1out R1in P3.0 10 3
3 4
RxD
T2in T2out
1 18
R2out R2int
DB-9
20 19

TTL side 6 9 RS232 side


To allow data transfer between the PC
SERIAL and an 8051 system without any error,
COMMUNICA- we must make sure that the baud rate
TION of 8051 system matches the baud rate
PROGRAMMING of the PC’s COM port
Hyperterminal function supports baud
rates much higher than listed below
PC Baud Rates
110
150
300
600
1200
2400
4800
9600
19200 Baud rates supported by
486/Pentium IBM PC BIOS

With XTAL = 11.0592 MHz, find the TH1 value needed to have the
following baud rates. (a) 9600 (b) 2400 (c) 1200
SERIAL Solution:
COMMUNICA- The machine cycle frequency of 8051 = 11.0592 / 12 = 921.6 kHz,
TION and 921.6 kHz / 32 = 28,800 Hz is frequency by UART to timer 1 to
set baud rate.
PROGRAMMING (a) 28,800 / 3 = 9600 where -3 = FD (hex) is loaded into TH1
(cont’) (b) 28,800 / 12 = 2400 where -12 = F4 (hex) is loaded into TH1
(c) 28,800 / 24 = 1200 where -24 = E8 (hex) is loaded into TH1
Notice that dividing 1/12 of the crystal frequency by 32 is the default
value upon activation of the 8051 RESET pin.
11.0592 MHz

Machine cycle freq 28800 Hz
XTAL ÷ 32
÷ 12
oscillator 921.6 kHz By UART To timer 1
To set the
Baud rate
Baud Rate TH1 (Decimal) TH1 (Hex)
9600 -3 FD
TF is set to 1 every 12 4800 -6 FA
ticks, so it functions as 2400 -12 F4
a frequency divider 1200 -24 E8


SBUF is an 8-bit register used solely for
SERIAL serial communication
COMMUNICA- For a byte data to be transferred via the
TION TxD line, it must be placed in the SBUF
PROGRAMMING register
The moment a byte is written into SBUF, it is
framed with the start and stop bits and
SBUF Register transferred serially via the TxD line
SBUF holds the byte of data when it is
received by 8051 RxD line
When the bits are received serially via RxD, the
8051 deframes it by eliminating the stop and
start bits, making a byte out of the data received,
and then placing it in SBUF

MOV SBUF,#’D’ ;load SBUF=44h, ASCII for ‘D’
MOV SBUF,A ;copy accumulator into SBUF
MOV A,SBUF ;copy SBUF into accumulator


SCON is an 8-bit register used to
SERIAL program the start bit, stop bit, and data
COMMUNICA- bits of data framing, among other
TION things
PROGRAMMING
SM0 SM1 SM2 REN TB8 RB8 TI RI
SCON Register
SM0 SCON.7 Serial port mode specifier
SM1 SCON.6 Serial port mode specifier
SM2 SCON.5 Used for multiprocessor communication
REN SCON.4 Set/cleared by software to enable/disable reception
TB8 SCON.3 Not widely used
RB8 SCON.2 Not widely used
TI SCON.1 Transmit interrupt flag. Set by HW at the
begin of the stop bit mode 1. And cleared by SW
RI SCON.0 Receive interrupt flag. Set by HW at the
begin of the stop bit mode 1. And cleared by SW

Note: Make SM2, TB8, and RB8 =0


SM0, SM1
SERIAL
COMMUNICA- They determine the framing of data by
TION specifying the number of bits per character,
PROGRAMMING and the start and stop bits
SM0 SM1
0 0 Serial Mode 0
SCON Register Serial Mode 1, 8-bit data,
0 1
(cont’) 1 stop bit, 1 start bit
1 0 Serial Mode 2
Only mode 1 is
1 1 Serial Mode 3
of interest to us
SM2
This enables the multiprocessing capability
of the 8051


REN (receive enable)
It is a bit-adressable register
SERIAL When it is high, it allows 8051 to receive data on
COMMUNICA- RxD pin
TION If low, the receiver is disable
PROGRAMMING TI (transmit interrupt)
When 8051 finishes the transfer of 8-bit
SCON Register character
(cont’) It raises TI flag to indicate that it is ready to
transfer another byte
TI bit is raised at the beginning of the stop bit
RI (receive interrupt)
When 8051 receives data serially via RxD, it
gets rid of the start and stop bits and
places the byte in SBUF register
It raises the RI flag bit to indicate that a byte
has been received and should be picked up
before it is lost
RI is raised halfway through the stop bit

In programming the 8051 to transfer
character bytes serially
SERIAL
1. TMOD register is loaded with the value
COMMUNICA- 20H, indicating the use of timer 1 in mode
TION 2 (8-bit auto-reload) to set baud rate
PROGRAMMING 2. The TH1 is loaded with one of the values
to set baud rate for serial data transfer
Programming 3. The SCON register is loaded with the value
Serial Data 50H, indicating serial mode 1, where an 8-
bit data is framed with start and stop bits
Transmitting
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred
serially is written into SBUF register
7. The TI flag bit is monitored with the use of
instruction JNB TI,xx to see if the
character has been transferred completely
8. To transfer the next byte, go to step 5

Write a program for the 8051 to transfer letter “A” serially at 4800
SERIAL baud, continuously.
COMMUNICA-
TION Solution:
MOV TMOD,#20H ;timer 1,mode 2(auto reload)
PROGRAMMING MOV TH1,#-6 ;4800 baud rate
MOV SCON,#50H ;8-bit, 1 stop, REN enabled
SETB TR1 ;start timer 1
Programming AGAIN: MOV SBUF,#”A” ;letter “A” to transfer
Serial Data HERE: JNB
CLR
TI,HERE
TI
;wait for the last bit
;clear TI for next char
Transmitting SJMP AGAIN ;keep sending A
(cont’)


Write a program for the 8051 to transfer “YES” serially at 9600
SERIAL baud, 8-bit data, 1 stop bit, do this continuously
COMMUNICA-
TION Solution:
Programming AGAIN: MOV A,#”Y” ;transfer “Y”
Serial Data ACALL TRANS
MOV A,#”E” ;transfer “E”
Transmitting ACALL TRANS
(cont’) MOV A,#”S” ;transfer “S”
ACALL TRANS
SJMP AGAIN ;keep doing it
;serial data transfer subroutine
TRANS: MOV SBUF,A ;load SBUF
HERE: JNB TI,HERE ;wait for the last bit
CLR TI ;get ready for next byte
RET


The steps that 8051 goes through in
SERIAL transmitting a character via TxD
COMMUNICA- 1. The byte character to be transmitted is
TION written into the SBUF register
PROGRAMMING 2. The start bit is transferred
3. The 8-bit character is transferred on bit at
a time
Importance of 4. The stop bit is transferred
TI Flag It is during the transfer of the stop bit that
8051 raises the TI flag, indicating that the last
character was transmitted
5. By monitoring the TI flag, we make sure
that we are not overloading the SBUF
If we write another byte into the SBUF before
TI is raised, the untransmitted portion of the
previous byte will be lost
6. After SBUF is loaded with a new byte, the
TI flag bit must be forced to 0 by CLR TI
in order for this new byte to be transferred

By checking the TI flag bit, we know
SERIAL whether or not the 8051 is ready to
COMMUNICA-
transfer another byte
TION
It must be noted that TI flag bit is raised by
PROGRAMMING
8051 itself when it finishes data transfer
It must be cleared by the programmer with
Importance of instruction CLR TI
TI Flag
(cont’) If we write a byte into SBUF before the TI
flag bit is raised, we risk the loss of a
portion of the byte being transferred
The TI bit can be checked by
The instruction JNB TI,xx
Using an interrupt


In programming the 8051 to receive
SERIAL character bytes serially
COMMUNICA- 1. TMOD register is loaded with the value
TION 20H, indicating the use of timer 1 in mode
PROGRAMMING 2 (8-bit auto-reload) to set baud rate
2. TH1 is loaded to set baud rate
Programming 3. The SCON register is loaded with the value
50H, indicating serial mode 1, where an 8-
Serial Data bit data is framed with start and stop bits
Receiving 4. TR1 is set to 1 to start timer 1
5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of
instruction JNB RI,xx to see if an entire
character has been received yet
7. When RI is raised, SBUF has the byte, its
contents are moved into a safe place
8. To receive the next character, go to step 5

Write a program for the 8051 to receive bytes of data serially, and
SERIAL put them in P1, set the baud rate at 4800, 8-bit data, and 1 stop bit
COMMUNICA-
TION Solution:
Programming HERE: JNB RI,HERE ;wait for char to come in
Serial Data MOV
MOV
A,SBUF
P1,A
;saving incoming byte in A
;send to port 1
Receiving CLR RI ;get ready to receive next
(cont’) ;byte
SJMP HERE ;keep getting data


Example 10-5
Assume that the 8051 serial port is connected to the COM port of
SERIAL IBM PC, and on the PC, we are using the terminal.exe program to
COMMUNICA- send and receive data serially. P1 and P2 of the 8051 are connected
to LEDs and switches, respectively. Write an 8051 program to (a)
TION send to PC the message “We Are Ready”, (b) receive any data send
PROGRAMMING by PC and put it on LEDs connected to P1, and (c) get data on
switches connected to P2 and send it to PC serially. The program
should perform part (a) once, but parts (b) and (c) continuously, use
Programming 4800 baud rate.
Serial Data
Receiving Solution:
ORG 0
(cont’) MOV P2,#0FFH ;make P2 an input port
MOV TMOD,#20H ;timer 1, mode 2
MOV TH1,#0FAH ;4800 baud rate
MOV DPTR,#MYDATA ;load pointer for message
H_1: CLR A
MOV A,@A+DPTR ;get the character
...



SERIAL JZ B_1 ;if last character get out
COMMUNICA- ACALL SEND
INC DPTR
;otherwise call transfer
;next one
TION SJMP H_1 ;stay in loop
PROGRAMMING B_1: MOV a,P2
ACALL SEND
;read data on P2
;transfer it serially
ACALL RECV ;get the serial data
Programming MOV P1,A
SJMP B_1
;display it on LEDs
;stay in loop indefinitely
Serial Data ;----serial data transfer. ACC has the data------
Receiving SEND: MOV SBUF,A ;load the data
H_2: JNB TI,H_2 ;stay here until last bit
(cont’) ;gone
CLR TI ;get ready for next char
RET ;return to caller
;----Receive data serially in ACC----------------
RECV: JNB RI,RECV ;wait here for char
MOV A,SBUF ;save it in ACC
CLR RI ;get ready for next char
RET ;return to caller
...


SERIAL
COMMUNICA- ;-----The message---------------
TION
MYDATA: DB “We Are Ready”,0
END
PROGRAMMING
8051
LED
Programming To PC TxD
P1

Serial Data
Receiving COM Port RxD
P2 SW
(cont’)


In receiving bit via its RxD pin, 8051
SERIAL goes through the following steps
COMMUNICA-
1. It receives the start bit
TION
Indicating that the next bit is the first bit of the
PROGRAMMING character byte it is about to receive
2. The 8-bit character is received one bit at
Importance of time
RI Flag 3. The stop bit is received
When receiving the stop bit 8051 makes RI = 1,
indicating that an entire character byte has
been received and must be picked up before it
gets overwritten by an incoming character


(cont’)
SERIAL 4. By checking the RI flag bit when it is
COMMUNICA- raised, we know that a character has been
TION received and is sitting in the SBUF register
PROGRAMMING We copy the SBUF contents to a safe place in
some other register or memory before it is lost

Importance of 5. After the SBUF contents are copied into a
safe place, the RI flag bit must be forced
RI Flag to 0 by CLR RI in order to allow the next
(cont’)
received character byte to be placed in
SBUF
Failure to do this causes loss of the received
character


By checking the RI flag bit, we know
SERIAL whether or not the 8051 received a
COMMUNICA- character byte
TION If we failed to copy SBUF into a safe place,
PROGRAMMING we risk the loss of the received byte
It must be noted that RI flag bit is raised by
Importance of 8051 when it finish receive data
RI Flag It must be cleared by the programmer with
(cont’)
instruction CLR RI
If we copy SBUF into a safe place before
the RI flag bit is raised, we risk copying
garbage
The RI bit can be checked by
The instruction JNB RI,xx
Using an interrupt


There are two ways to increase the
SERIAL
COMMUNICA- baud rate of data transfer The system
crystal is fixed
TION To use a higher frequency crystal
PROGRAMMING To change a bit in the PCON register
PCON register is an 8-bit register
Doubling Baud
Rate When 8051 is powered up, SMOD is zero
We can set it to high by software and
thereby double the baud rate
SMOD -- -- -- GF1 GF0 PD IDL

It is not a bit- MOV A,PCON ;place a copy of PCON in ACC
addressable SETB ACC.7 ;make D7=1
MOV PCON,A ;changing any other bits
register


SERIAL 11.0592 MHz SMOD = 1 57600 Hz
÷ 16
COMMUNICA- XTAL
Machine cycle freq To timer
1 To set
TION oscillator
÷ 12
921.6 kHz 28800 Hz the Baud
÷ 32 rate
PROGRAMMING SMOD = 0

Doubling Baud Baud Rate comparison for SMOD=0 and SMOD=1
Rate
TH1 (Decimal) (Hex) SMOD=0 SMOD=1
(cont’)
-3 FD 9600 19200
-6 FA 4800 9600
-12 F4 2400 4800
-24 E8 1200 2400


Example 10-6
SERIAL Assume that XTAL = 11.0592 MHz for the following program,
COMMUNICA- state (a) what this program does, (b) compute the frequency used
by timer 1 to set the baud rate, and (c) find the baud rate of the data
TION transfer.
PROGRAMMING
MOV A,PCON ;A=PCON
MOV ACC.7 ;make D7=1
Doubling Baud MOV PCON,A ;SMOD=1, double baud rate
Rate MOV TMOD,#20H
;with same XTAL freq.
;timer 1, mode 2
(cont’) MOV TH1,-3 ;19200 (57600/3 =19200)
MOV SCON,#50H ;8-bit data, 1 stop bit, RI
;enabled
MOV A,#”B” ;transfer letter B
A_1: CLR TI ;make sure TI=0
MOV SBUF,A ;transfer it
H_1: JNB TI,H_1 ;stay here until the last
;bit is gone
SJMP A_1 ;keep sending “B” again



SERIAL Solution:
COMMUNICA- (a) This program transfers ASCII letter B (01000010
binary) continuously
TION (b) With XTAL = 11.0592 MHz and SMOD = 1 in the
PROGRAMMING above program, we have:

11.0592 / 12 = 921.6 kHz machine cycle frequency.
Doubling Baud 921.6 / 16 = 57,600 Hz frequency used by timer 1
to set the baud rate.
Rate 57600 / 3 = 19,200, the baud rate.
(cont’)
Find the TH1 value (in both decimal and hex ) to set the baud rate
to each of the following. (a) 9600 (b) 4800 if SMOD=1. Assume
that XTAL 11.0592 MHz

Solution:
With XTAL = 11.0592 and SMOD = 1, we have timer frequency =
57,600 Hz.
(a) 57600 / 9600 = 6; so TH1 = -6 or TH1 = FAH
(b) 57600 / 4800 = 12; so TH1 = -12 or TH1 = F4H


Example 10-8
SERIAL Find the baud rate if TH1 = -2, SMOD = 1, and XTAL = 11.0592
COMMUNICA- MHz. Is this baud rate supported by IBM compatible PCs?

TION Solution:
PROGRAMMING With XTAL = 11.0592 and SMOD = 1, we have timer frequency =
57,600 Hz. The baud rate is 57,600/2 = 28,800. This baud rate is
not supported by the BIOS of the PCs; however, the PC can be
Doubling Baud programmed to do data transfer at such a speed. Also,
Rate HyperTerminal in Windows supports this and other baud rates.
(cont’)


Example 10-10
Write a program to send the message “The Earth is but One
SERIAL Country” to serial port. Assume a SW is connected to pin P1.2.
COMMUNICA- Monitor its status and set the baud rate as follows:
SW = 0, 4800 baud rate
TION SW = 1, 9600 baud rate
PROGRAMMING Assume XTAL = 11.0592 MHz, 8-bit data, and 1 stop bit.

Solution:
Doubling Baud SW BIT P1.2
Rate MAIN:
ORG 0H ;starting position

(cont’) MOV TMOD,#20H
MOV TH1,#-6 ;4800 baud rate (default)
MOV SCON,#50H
SETB TR1
SETB SW ;make SW an input
S1: JNB SW,SLOWSP ;check SW status
MOV A,PCON ;read PCON
SETB ACC.7 ;set SMOD high for 9600
MOV PCON,A ;write PCON
SJMP OVER ;send message
.....


.....
SERIAL
COMMUNICA- SLOWSP:
MOV A,PCON ;read PCON
TION SETB ACC.7 ;set SMOD low for 4800
MOV PCON,A ;write PCON
PROGRAMMING OVER: MOV DPTR,#MESS1 ;load address to message
FN: CLR A
MOVC A,@A+DPTR ;read value
Doubling Baud JZ S1 ;check for end of line
ACALL SENDCOM ;send value to serial port
Rate INC DPTR ;move to next value
(cont’) SJMP FN ;repeat
;------------
SENDCOM:
MOV SBUF,A ;place value in buffer
HERE: JNB TI,HERE ;wait until transmitted
CLR TI ;clear
RET ;return

;------------
MESS1: DB “The Earth is but One Country”,0
END


Many new generations of 8051
PROGRAMMING
THE SECOND
microcontroller come with two serial
SERIAL PORT ports, like DS89C4x0 and DS80C320
The second serial port of DS89C4x0 uses
pins P1.2 and P1.3 for the Rx and Tx lines
The second serial port uses some reserved
SFR addresses for the SCON and SBUF
There is no universal agreement among the
makers as to which addresses should be used
– The SFR addresses of C0H and C1H are set
aside for SBUF and SCON of DS89C4x0
The DS89C4x0 technical documentation refers
to these registers as SCON1 and SBUF1
The first ones are designated as SCON0
and SBUF0

DS89C4x0 pin diagram
PROGRAMMING
THE SECOND (T2) P1.0 1 40 Vcc
(T2EX) P1.1 2 39 P0.0 (AD0)
SERIAL PORT (RXD1) P1.2 3 38 P0.1 (AD1)

(cont’) (TXD1) P1.3 4 37 P0.2 (AD2)
(INT2) P1.4 5 36 P0.3 (AD3)
(-INT3) P1.5 6 35 P0.4 (AD4)
(INT4) P1.6 7 34 P0.5 (AD5)
(-INT5) P1.7 8 DS89C4x0 33 P0.6 (AD6)
RST 9 (89C420 32 P0.7 (AD7)
31 -EA/VPP
(RXD) P3.0
(TXD) P3.1
10
89C430 30 ALE/-PROG
11
(-INT0) P3.2 12 89C440 29 -PSEN
(-INT1) P3.3 13 89C450) 28 P2.7 (A15)
P2.6 (A14)
(T0) P3.4 14 27
(T1) P3.5 15 26 P2.5 (A13)
(-WR) P3.6 16 25 P2.4 (A12)
(-RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)


PROGRAMMING
THE SECOND
SERIAL PORT SFR Byte Addresses for DS89C4x0 Serial Ports
(cont’)
SFR First Serial Port Second Serial Port
(byte address)
SCON SCON0 = 98H SCON1 = C0H
SBUF SBUF0 = 99H SBUF1 = C1H
TL TL1 = 8BH TL1 = 8BH
TH TH1 = 8DH TH1 = 8DH
TCON TCON0 = 88H TCON0 = 88H
PCON PCON = 87H PCON = 87H


Upon reset, DS89c4x0 uses Timer 1 for
PROGRAMMING
THE SECOND
setting baud rate of both serial ports
SERIAL PORT While each serial port has its own SCON
(cont’) and SBUF registers, both ports can use
Timer1 for setting the baud rate
SBUF and SCON refer to the SFR registers
of the first serial port
Since the older 8051 assemblers do not support
this new second serial port, we need to define
them in program
To avoid confusion, in DS89C4x0 programs we
use SCON0 and SBUF0 for the first and SCON1
and SBUF1for the second serial ports


Example 10-11
Write a program for the second serial port of the DS89C4x0 to
PROGRAMMING continuously transfer the letter “A” serially at 4800 baud. Use 8-bit
THE SECOND data and 1 stop bit. Use Timer 1.

SERIAL PORT Solution:
(cont’) SBUF1 EQU 0C1H ;2nd serial SBUF addr
SCON1 EQU 0C0H ;2nd serial SCON addr
TI1 BIT 0C1H ;2nd serial TI bit addr
RI1 BIT 0C0H ;2nd serial RI bit addr
MAIN:
MOV TMOD,#20H ;COM2 uses Timer 1 on reset
MOV TH1,#-6 ;4800 baud rate
MOV SCON1,#50H ;8-bit, 1 stop, REN enabled
AGAIN:MOV A,#”A” ;send char ‘A’
ACALL SENDCOM2
SJMP AGAIN
SENDCOM2:
MOV SBUF1,A ;COM2 has its own SBUF
HERE: JNB TI1,HERE ;COM2 has its own TI flag
CLR TI1
RET
END


Example 10-14
Assume that a switch is connected to pin P2.0. Write a program to
PROGRAMMING monitor the switch and perform the following:
(a) If SW = 0, send the message “Hello” to the Serial #0 port
THE SECOND (b) If SW = 1, send the message “Goodbye” to the Serial #1 port.
SERIAL PORT Solution:
(cont’) SCON1 EQU 0C0H
TI1 BIT 0C1H
SW1 BIT P2.0
MOV TMOD,#20H
MOV TH1,#-3 ;9600 baud rate
MOV SCON,#50H
MOV SCON1,#50H
SETB TR1
SETB SW1 ;make SW1 an input
S1: JB SW1,NEXT ;check SW1 status
MOV DPTR,#MESS1;if SW1=0 display “Hello”
FN: CLR A
JZ S1 ;check for end of line
ACALL SENDCOM1 ;send to serial port
INC DPTR ;move to next value
SJM FN
.....

.....

PROGRAMMING NEXT: MOV DPTR,#MESS2;if SW1=1 display “Goodbye”
THE SECOND LN: CLR A
SERIAL PORT JZ S1 ;check for end of line
ACALL SENDCOM2 ;send to serial port
(cont’) INC DPTR ;move to next value
SJM LN

SENDCOM1:
MOV SBUF,A ;place value in buffer
HERE: JNB TI,HERE ;wait until transmitted
CLR TI ;clear
RET
;------------
SENDCOM2:
MOV SBUF1,A ;place value in buffer
HERE1: JNB TI1,HERE1 ;wait until transmitted
CLR TI1 ;clear
RET

MESS1: DB “Hello”,0
MESS2: DB “Goodbye”,0
END


Example 10-15
SERIAL PORT Write a C program for 8051 to transfer the letter “A” serially at 4800
PROGRAMMING baud continuously. Use 8-bit data and 1 stop bit.
IN C Solution:
#include <reg51.h>
void main(void){
Transmitting TMOD=0x20; //use Timer 1, mode 2
and Receiving TH1=0xFA;
SCON=0x50;
//4800 baud rate

Data TR1=1;
while (1) {
SBUF=‘A’; //place value in buffer
while (TI==0);
TI=0;
}
}


Example 10-16
SERIAL PORT Write an 8051 C program to transfer the message “YES” serially at
PROGRAMMING 9600 baud, 8-bit data, 1 stop bit. Do this continuously.
IN C Solution:
#include <reg51.h>
void SerTx(unsigned char);
Transmitting void main(void){
and Receiving TMOD=0x20;
TH1=0xFD;
//use Timer 1, mode 2
//9600 baud rate
Data SCON=0x50;
TR1=1; //start timer
(cont’) while (1) {
SerTx(‘Y’);
SerTx(‘E’);
SerTx(‘S’);
}
}
void SerTx(unsigned char x){
SBUF=x; //place value in buffer
while (TI==0); //wait until transmitted
TI=0;
}


Example 10-17
SERIAL PORT Program the 8051 in C to receive bytes of data serially and put them
PROGRAMMING in P1. Set the baud rate at 4800, 8-bit data, and 1 stop bit.
IN C Solution:
#include <reg51.h>
void main(void){
Transmitting unsigned char mybyte;
and Receiving TMOD=0x20;
TH1=0xFA;
//use Timer 1, mode 2
//4800 baud rate
Data SCON=0x50;
(cont’) while (1) { //repeat forever
while (RI==0); //wait to receive
mybyte=SBUF; //save value
P1=mybyte; //write value to port
RI=0;
}
}


Example 10-19
SERIAL PORT Write an 8051 C Program to send the two messages “Normal Speed”
PROGRAMMING and “High Speed” to the serial port. Assuming that SW is connected
to pin P2.0, monitor its status and set the baud rate as follows:
IN C SW = 0, 28,800 baud rate
SW = 1, 56K baud rate
Assume that XTAL = 11.0592 MHz for both cases.
Transmitting
and Receiving Solution:
#include <reg51.h>
Data sbit MYSW=P2^0; //input switch
void main(void){
unsigned char Mess1[]=“Normal Speed”;
unsigned char Mess2[]=“High Speed”;
TMOD=0x20; //use Timer 1, mode 2
TH1=0xFF; //28800 for normal
SCON=0x50;
.....


.....
SERIAL PORT if(MYSW==0) {
PROGRAMMING for (z=0;z<12;z++) {
IN C SBUF=Mess1[z]; //place value in buffer
while(TI==0); //wait for transmit
TI=0;
Transmitting }
and Receiving }
else {
Data PCON=PCON|0x80; //for high speed of 56K
(cont’) for (z=0;z<10;z++) {
SBUF=Mess2[z]; //place value in buffer
while(TI==0); //wait for transmit
TI=0;
}
}
}


Example 10-20
SERIAL PORT Write a C program for the DS89C4x0 to transfer the letter “A” serially
PROGRAMMING at 4800 baud continuously. Use the second serial port with 8-bit data
and 1 stop bit. We can only use Timer 1 to set the baud rate.
IN C
Solution:
#include <reg51.h>
C Compilers sfr SBUF1=0xC1;
and the Second sfr SCON1=0xC0;
sbit TI1=0xC1;
Serial Port void main(void){
TH1=0xFA; //4800 baud rate
SCON=0x50; //use 2nd serial port SCON1
while (1) {
SBUF1=‘A’; //use 2nd serial port SBUF1
while (TI1==0); //wait for transmit
TI1=0;
}
}


Example 10-21
SERIAL PORT Program the DS89C4x0 in C to receive bytes of data serially via the
PROGRAMMING second serial port and put them in P1. Set the baud rate at 9600, 8-bit
data and 1 stop bit. Use Timer 1 for baud rate generation.
IN C
Solution:
#include <reg51.h>
C Compilers sfr SBUF1=0xC1;
and the Second sfr SCON1=0xC0;
sbit RI1=0xC0;
Serial Port void main(void){
TH1=0xFD; //9600 baud rate
SCON1=0x50; //use 2nd serial port SCON1
while (1) {
while (RI1==0); //monitor RI1
mybyte=SBUF1; //use SBUF1
P2=mybyte; //place value on port
RI1=0;
}
}


INTERRUPTS
PROGRAMMING


Chung-Ping Young
楊中平


An interrupt is an external or internal
INTERRUPTS event that interrupts the
microcontroller to inform it that a
Interrupts vs.
device needs its service
Polling
A single microcontroller can serve
several devices by two ways
Interrupts
Whenever any device needs its service, the
device notifies the microcontroller by sending it
an interrupt signal
Upon receiving an interrupt signal, the
microcontroller interrupts whatever it is doing
and serves the device
The program which is associated with the
interrupt is called the interrupt service routine
(ISR) or interrupt handler


(cont’)
INTERRUPTS
Polling
The microcontroller continuously monitors the
Interrupts vs. status of a given device
Polling When the conditions met, it performs the
(cont’) service
After that, it moves on to monitor the next
device until every one is serviced
Polling can monitor the status of
several devices and serve each of
them as certain conditions are met
The polling method is not efficient, since it
wastes much of the microcontroller’s time
by polling devices that do not need service
ex. JNB TF,target


The advantage of interrupts is that the
INTERRUPTS
microcontroller can serve many
Interrupts vs. devices (not all at the same time)
Polling Each devices can get the attention of the
(cont’) microcontroller based on the assigned
priority
For the polling method, it is not possible to
assign priority since it checks all devices in
a round-robin fashion
The microcontroller can also ignore
(mask) a device request for service
This is not possible for the polling method


For every interrupt, there must be an
INTERRUPTS
interrupt service routine (ISR), or
Interrupt interrupt handler
Service Routine When an interrupt is invoked, the micro-
controller runs the interrupt service
routine
For every interrupt, there is a fixed

location in memory that holds the address
of its ISR
The group of memory locations set aside
to hold the addresses of ISRs is called
interrupt vector table


Upon activation of an interrupt, the
INTERRUPTS
microcontroller goes through the
Steps in following steps
Executing an 1. It finishes the instruction it is executing
Interrupt and saves the address of the next
instruction (PC) on the stack
2. It also saves the current status of all the
interrupts internally (i.e: not on the stack)
3. It jumps to a fixed location in memory,
called the interrupt vector table, that
holds the address of the ISR


(cont’)
INTERRUPTS 4. The microcontroller gets the address of
the ISR from the interrupt vector table
Steps in and jumps to it
Executing an It starts to execute the interrupt service
Interrupt subroutine until it reaches the last instruction
(cont’) of the subroutine which is RETI (return from
interrupt)
5. Upon executing the RETI instruction, the
microcontroller returns to the place
where it was interrupted
First, it gets the program counter (PC)
address from the stack by popping the top
two bytes of the stack into the PC
Then it starts to execute from that address


Six interrupts are allocated as follows
INTERRUPTS
Reset – power-up reset
Six Interrupts Two interrupts are set aside for the timers:
in 8051 one for timer 0 and one for timer 1
Two interrupts are set aside for hardware
external interrupts
P3.2 and P3.3 are for the external hardware
interrupts INT0 (or EX1), and INT1 (or EX2)
Serial communication has a single
interrupt that belongs to both receive and
transfer


INTERRUPTS Interrupt vector table
Interrupt ROM Location Pin
(hex)
Six Interrupts Reset 0000 9
in 8051 External HW (INT0) 0003 P3.2 (12)
(cont’) Timer 0 (TF0) 000B
External HW (INT1) 0013 P3.3 (13)
Timer 1 (TF1) 001B
Serial COM (RI and TI) 0023

ORG 0 ;wake-up ROM reset location
LJMP MAIN ;by-pass int. vector table
;---- the wake-up program
ORG 30H
MAIN: Only three bytes of ROM space
.... assigned to the reset pin. We put
the LJMP as the first instruction
END and redirect the processor away
from the interrupt vector table.


Upon reset, all interrupts are disabled
INTERRUPTS
(masked), meaning that none will be
Enabling and responded to by the microcontroller if
Disabling an they are activated
Interrupt The interrupts must be enabled by
software in order for the
microcontroller to respond to them
There is a register called IE (interrupt
enable) that is responsible for enabling
(unmasking) and disabling (masking) the
interrupts


IE (Interrupt Enable) Register
INTERRUPTS
D7 D0
EA -- ET2 ES ET1 EX1 ET0 EX0
Enabling and
Disabling an EA (enable all) must be set to 1 in order
Interrupt for rest of the register to take effect

(cont’) EA IE.7 Disables all interrupts
-- IE.6 Not implemented, reserved for future use
ET2 IE.5 Enables or disables timer 2 overflow or capture
interrupt (8952)
ES IE.4 Enables or disables the serial port interrupt
ET1 IE.3 Enables or disables timer 1 overflow interrupt
EX1 IE.2 Enables or disables external interrupt 1
ET0 IE.1 Enables or disables timer 0 overflow interrupt
EX0 IE.0 Enables or disables external interrupt 0


To enable an interrupt, we take the
INTERRUPTS
following steps:
Enabling and 1. Bit D7 of the IE register (EA) must be set
Disabling an to high to allow the rest of register to
Interrupt take effect
(cont’) 2. The value of EA
If EA = 1, interrupts are enabled and will be
responded to if their corresponding bits in IE
are high
If EA = 0, no interrupt will be responded to,
even if the associated bit in the IE register is
high


Example 11-1
INTERRUPTS Show the instructions to (a) enable the serial interrupt, timer 0
interrupt, and external hardware interrupt 1 (EX1),and (b) disable
Enabling and (mask) the timer 0 interrupt, then (c) show how to disable all the
interrupts with a single instruction.
Disabling an
Interrupt Solution:

(cont’) (a) MOV IE,#10010110B ;enable serial,
;timer 0, EX1
Another way to perform the same manipulation is
SETB IE.7 ;EA=1, global enable
SETB IE.4 ;enable serial interrupt
SETB IE.1 ;enable Timer 0 interrupt
SETB IE.2 ;enable EX1
(b) CLR IE.1 ;mask (disable) timer 0
;interrupt only
(c) CLR IE.7 ;disable all interrupts


The timer flag (TF) is raised when the
TIMER timer rolls over
INTERRUPTS In polling TF, we have to wait until the TF
is raised
The problem with this method is that the
microcontroller is tied down while waiting for TF
to be raised, and can not do anything else
Using interrupts solves this problem and,
avoids tying down the controller
If the timer interrupt in the IE register is
enabled, whenever the timer rolls over, TF is
raised, and the microcontroller is interrupted in
whatever it is doing, and jumps to the interrupt
vector table to service the ISR
In this way, the microcontroller can do other
until it is notified that the timer has rolled over
TF0 Timer 0 Interrupt Vector TF1 Timer 1 Interrupt Vector
1 000BH 1 001BH
Jumps to Jumps to

Example 11-2
TIMER Write a program that continuously get 8-bit data from P0 and sends it
to P1 while simultaneously creating a square wave of 200 μs period
INTERRUPTS on pin P2.1. Use timer 0 to create the square wave. Assume that
(cont’) XTAL = 11.0592 MHz.
Solution:
We will use timer 0 in mode 2 (auto reload). TH0 = 100/1.085 us = 92
;--upon wake-up go to main, avoid using
;memory allocated to Interrupt Vector Table
ORG 0000H
LJMP MAIN ;by-pass interrupt vector table
;
;--ISR for timer 0 to generate square wave
ORG 000BH ;Timer 0 interrupt vector table
CPL P2.1 ;toggle P2.1 pin
RETI ;return from ISR
...


...
TIMER ;--The main program for initialization
INTERRUPTS ORG 0030H ;after vector table space
(cont’) MAIN: MOV TMOD,#02H ;Timer 0, mode 2
MOV TH0,#-92 ;TH0=A4H for -92
MOV IE,#82H ;IE=10000010 (bin) enable
;Timer 0
SETB TR0 ;Start Timer 0
BACK: MOV A,P0 ;get data from P0
MOV P1,A ;issue it to P1
SJMP BACK ;keep doing it loop
;unless interrupted by TF0
END


Example 11-3
TIMER Rewrite Example 11-2 to create a square wave that has a high portion
of 1085 us and a low portion of 15 us. Assume XTAL=11.0592MHz.
INTERRUPTS Use timer 1.
(cont’)
Solution:
Since 1085 us is 1000 × 1.085 we need to use mode 1 of timer 1.
;--upon wake-up go to main, avoid using
;memory allocated to Interrupt Vector Table
ORG 0000H
LJMP MAIN ;by-pass int. vector table
;--ISR for timer 1 to generate square wave
ORG 001BH ;Timer 1 int. vector table
LJMP ISR_T1 ;jump to ISR
...


...
;--The main program for initialization
TIMER ORG 0030H ;after vector table space
MAIN: MOV TMOD,#10H ;Timer 1, mode 1
INTERRUPTS MOV P0,#0FFH ;make P0 an input port
(cont’) MOV TL1,#018H ;TL1=18 low byte of -1000
MOV TH1,#0FCH ;TH1=FC high byte of -1000
MOV IE,#88H ;10001000 enable Timer 1 int
SETB TR1 ;Start Timer 1
BACK: MOV A,P0 ;get data from P0 the pulse is
Low portion of
MOV P1,A ;issue it to by 14 MC
created P1
SJMP BACK ;keep doing1.085 us = 15.19 us
14 x it
;Timer 1 ISR. Must be reloaded, not auto-reload
ISR_T1: CLR TR1 ;stop Timer 1
MOV R2,#4 ; 2MC
CLR P2.1 ;P2.1=0, start of low portion
HERE: DJNZ R2,HERE ;4x2 machine cycle 8MC
MOV TL1,#18H ;load T1 low byte value 2MC
MOV TH1,#0FCH;load T1 high byte value 2MC
SETB TR1 ;starts timer1 1MC
SETB P2.1 ;P2.1=1,back to high 1MC
RETI ;return to main
END


Example 11-4
TIMER Write a program to generate a square wave if 50Hz frequency on pin
P1.2. This is similar to Example 9-12 except that it uses an interrupt
INTERRUPTS for timer 0. Assume that XTAL=11.0592 MHz
(cont’)
Solution:
ORG 0
LJMP MAIN
ORG 000BH ;ISR for Timer 0
CPL P1.2
MOV TL0,#00
MOV TH0,#0DCH
RETI
ORG 30H
;--------main program for initialization
MAIN:MOV TM0D,#00000001B ;Timer 0, Mode 1
MOV TL0,#00
MOV TH0,#0DCH
MOV IE,#82H ;enable Timer 0 interrupt
SETB TR0
HERE:SJMP HERE
END


The 8051 has two external hardware
EXTERNAL
HARDWARE
interrupts
INTERRUPTS Pin 12 (P3.2) and pin 13 (P3.3) of the 8051,
designated as INT0 and INT1, are used as
external hardware interrupts
The interrupt vector table locations 0003H and
0013H are set aside for INT0 and INT1
There are two activation levels for the
external hardware interrupts
Level trigged
Edge trigged


EXTERNAL Activation of INT0
HARDWARE Level-triggered
INTERRUPTS INT0
0
IT0
(cont’) (Pin 3.2)
1 IE0
0003

Edge-triggered (TCON.1)

Activation of INT1
Level-triggered
0
INT1 IT1 0013
(Pin 3.3)
1 IE1
Edge-triggered (TCON.3)


In the level-triggered mode, INT0 and
EXTERNAL INT1 pins are normally high
HARDWARE
If a low-level signal is applied to them, it
INTERRUPTS triggers the interrupt
Then the microcontroller stops whatever it
Level-Triggered is doing and jumps to the interrupt vector
Interrupt table to service that interrupt
The low-level signal at the INT pin must
be removed before the execution of the
last instruction of the ISR, RETI; otherwise,
another interrupt will be generated
This is called a level-triggered or level-
activated interrupt and is the default
mode upon reset of the 8051


Example 11-5
EXTERNAL Assume that the INT1 pin is connected to a switch that is normally
high. Whenever it goes low, it should turn on an LED. The LED is
HARDWARE connected to P1.3 and is normally off. When it is turned on it should
INTERRUPTS stay on for a fraction of a second. As long as the switch is pressed low,
the LED should stay on. Vcc

Level-Triggered Solution: P1.3 to LED

Interrupt
ORG 0000H INT1
LJMP MAIN ;by-pass interrupt
(cont’) ;vector table
;--ISR for INT1 to turn on LED
ORG 0013H ;INT1 ISR
SETB P1.3 ;turn on LED
MOV R3,#255
Pressing the switch
BACK: DJNZ R3,BACK ;keep LED on for a while
CLR P1.3 ;turn off the LED will cause the LED
RETI ;return from ISR to be turned on. If
it is kept activated,
;--MAIN program for initialization the LED stays on
ORG 30H
MAIN: MOV IE,#10000100B ;enable external INT 1
HERE: SJMP HERE ;stay here until get interrupted
END


Pins P3.2 and P3.3 are used for normal
EXTERNAL I/O unless the INT0 and INT1 bits in
HARDWARE the IE register are enabled
INTERRUPTS
After the hardware interrupts in the IE
register are enabled, the controller keeps
Sampling Low sampling the INTn pin for a low-level signal
Level-Triggered once each machine cycle
Interrupt According to one manufacturer’s data sheet,
The pin must be held in a low state until the
start of the execution of ISR
If the INTn pin is brought back to a logic high
before the start of the execution of ISR there
will be no interrupt
If INTn pin is left at a logic low after the RETI
instruction of the ISR, another interrupt will be
activated after one instruction is executed


To ensure the activation of the hardware
EXTERNAL interrupt at the INTn pin, make sure that
HARDWARE the duration of the low-level signal is
INTERRUPTS around 4 machine cycles, but no more
This is due to the fact that the level-triggered
Sampling Low interrupt is not latched
Level-Triggered Thus the pin must be held in a low state until
Interrupt the start of the ISR execution
(cont’)
1 MC
4 machine cycles To INT0 or
1.085us INT1 pins
4 × 1.085us
note: On reset, IT0 (TCON.0) and IT1 (TCON.2) are both
low, making external interrupt level-triggered


To make INT0 and INT1 edge-
EXTERNAL
HARDWARE
triggered interrupts, we must program
INTERRUPTS the bits of the TCON register
The TCON register holds, among other bits,
Edge-Triggered the IT0 and IT1 flag bits that determine
Interrupt level- or edge-triggered mode of the
hardware interrupt
IT0 and IT1 are bits D0 and D2 of the TCON
register
They are also referred to as TCON.0 and
TCON.2 since the TCON register is bit-
addressable


TCON (Timer/Counter) Register (Bit-addressable)
EXTERNAL
D7 D0
HARDWARE
INTERRUPTS TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TF1 TCON.7 Timer 1 overflow flag. Set by
Edge-Triggered hardware when timer/counter
1 overflows. Cleared by hardware as
Interrupt the processor vectors to the interrupt
(cont’) service routine
TR1 TCON.6 Timer 1 run control bit. Set/cleared by
software to turn timer/counter 1 on/off
TF0 TCON.5 Timer 0 overflow flag. Set by
hardware when timer/counter 0
overflows. Cleared by hardware as the
processor vectors to the interrupt
service routine
TR0 TCON.4 Timer 0 run control bit. Set/cleared by
software to turn timer/counter 0 on/off

TCON (Timer/Counter) Register (Bit-addressable) (cont’)
EXTERNAL
HARDWARE IE1 TCON.3 External interrupt 1 edge flag. Set by
INTERRUPTS CPU when the external interrupt edge
(H-to-L transition) is detected. Cleared
by CPU when the interrupt is processed
Edge-Triggered
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared
Interrupt by software to specify falling edge/low-
(cont’) level triggered external interrupt
IE0 TCON.1 External interrupt 0 edge flag. Set by
CPU when the external interrupt edge
(H-to-L transition) is detected. Cleared
by CPU when the interrupt is processed
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared
by software to specify falling edge/low-
level triggered external interrupt


Assume that pin 3.3 (INT1) is connected to a pulse generator, write a
EXTERNAL program in which the falling edge of the pulse will send a high to
P1.3, which is connected to an LED (or buzzer). In other words, the
HARDWARE LED is turned on and off at the same rate as the pulses are applied to
INTERRUPTS the INT1 pin.
When the falling edge of the signal
is applied to pin INT1, the LED
Solution:
Edge-Triggered ORG 0000H
will be turned on momentarily.

Interrupt LJMP MAIN
(cont’) ;--ISR for hardware interrupt INT1 to turn on LED
ORG 0013H ;INT1 ISR
SETB P1.3 ;turn on LED
MOV R3,#255
BACK: DJNZ R3,BACK ;keep the buzzer on for a while
CLR P1.3 ;turn off the buzzer
The on-state duration
depends on the time
;------MAIN program for initialization
delay inside the ISR
ORG 30H
for INT1
MAIN: SETB TCON.2 ;make INT1 edge-triggered int.
MOV IE,#10000100B ;enable External INT 1
HERE: SJMP HERE ;stay here until get interrupted
END


In edge-triggered interrupts
EXTERNAL
HARDWARE The external source must be held high for
INTERRUPTS at least one machine cycle, and then held
low for at least one machine cycle
Sampling Edge- The falling edge of pins INT0 and INT1
Triggered are latched by the 8051 and are held by
Interrupt the TCON.1 and TCON.3 bits of TCON
register
Function as interrupt-in-service flags
It indicates that the interrupt is being serviced
now and on this INTn pin, and no new interrupt
will be responded to until this service is finished
Minimum pulse duration to
detect edge-triggered 1 MC 1 MC
interrupts XTAL=11.0592MHz 1.085us 1.085us


Regarding the IT0 and IT1 bits in the
EXTERNAL TCON register, the following two points
HARDWARE must be emphasized
INTERRUPTS
When the ISRs are finished (that is, upon
execution of RETI), these bits (TCON.1 and
Sampling Edge- TCON.3) are cleared, indicating that the
Triggered interrupt is finished and the 8051 is ready
Interrupt to respond to another interrupt on that pin
(cont’)
During the time that the interrupt service
routine is being executed, the INTn pin is
ignored, no matter how many times it
makes a high-to-low transition
RETI clears the corresponding bit in TCON
register (TCON.1 or TCON.3)
There is no need for instruction CLR TCON.1
before RETI in the ISR associated with INT0


Example 11-7
EXTERNAL What is the difference between the RET and RETI instructions?
Explain why we can not use RET instead of RETI as the last
HARDWARE instruction of an ISR.
INTERRUPTS
Solution:
Both perform the same actions of popping off the top two bytes of the
Sampling Edge- stack into the program counter, and marking the 8051 return to where
Triggered it left off.
Interrupt However, RETI also performs an additional task of clearing the
(cont’) interrupt-in-service flag, indicating that the servicing of the interrupt
is over and the 8051 now can accept a new interrupt on that pin. If
you use RET instead of RETI as the last instruction of the interrupt
service routine, you simply block any new interrupt on that pin after
the first interrupt, since the pin status would indicate that the interrupt
is still being serviced. In the cases of TF0, TF1, TCON.1, and
TCON.3, they are cleared due to the execution of RETI.


TI (transfer interrupt) is raised when
SERIAL
COMMUNI-
the last bit of the framed data, the
CATION stop bit, is transferred, indicating that
INTERRUPT the SBUF register is ready to transfer
the next byte
RI (received interrupt) is raised when
the entire frame of data, including the
stop bit, is received
In other words, when the SBUF register
has a byte, RI is raised to indicate that the
received byte needs to be picked up
before it is lost (overrun) by new incoming
serial data


In the 8051 there is only one interrupt
SERIAL
COMMUNI-
set aside for serial communication
CATION This interrupt is used to both send and
INTERRUPT receive data
If the interrupt bit in the IE register (IE.4)
RI and TI Flags is enabled, when RI or TI is raised the
and Interrupts 8051 gets interrupted and jumps to
memory location 0023H to execute the ISR
In that ISR we must examine the TI and RI
flags to see which one caused the interrupt
and respond accordingly
TI
0023H
RI
Serial interrupt is invoked by TI or RI flags

The serial interrupt is used mainly for
SERIAL
COMMUNI-
receiving data and is never used for
CATION sending data serially
INTERRUPT This is like getting a telephone call in
which we need a ring to be notified
Use of Serial If we need to make a phone call there are
COM in 8051 other ways to remind ourselves and there
is no need for ringing
However in receiving the phone call, we
must respond immediately no matter what
we are doing or we will miss the call


Example 11-8
Write a program in which the 8051 reads data from P1 and writes it to
SERIAL P2 continuously while giving a copy of it to the serial COM port to be
transferred serially. Assume that XTAL=11.0592. Set the baud rate at
COMMUNI- 9600.
CATION Solution:
INTERRUPT ORG 0000H
LJMP MAIN
ORG 23H
Use of Serial LJMP SERIAL ;jump to serial int ISR
COM in 8051
ORG 30H
MAIN: MOV P1,#0FFH ;make P1 an input port
(cont’) MOV TMOD,#20H ;timer 1, auto reload
MOV TH1,#0FDH ;9600 baud rate
MOV SCON,#50H ;8-bit,1 stop, ren enabled
MOV IE,10010000B ;enable serial int.
BACK: MOV A,P1 ;read data from port 1
MOV SBUF,A ;give a copy to SBUF
MOV P2,A ;send it to P2
SJMP BACK ;stay in loop indefinitely
...

...
;-----------------SERIAL PORT ISR
SERIAL ORG 100H
COMMUNI- SERIAL: JB TI,TRANS;jump if TI is high
CATION MOV A,SBUF ;otherwise due to receive
CLR RI ;clear RI since CPU doesn’t
INTERRUPT RETI ;return from ISR
TRANS: CLR TI ;clear TI since CPU doesn’t
Use of Serial RETI
END
;return from ISR

COM in 8051
(cont’) The moment a byte is written into SBUF it is framed and transferred
serially. As a result, when the last bit (stop bit) is transferred the TI is
raised, and that causes the serial interrupt to be invoked since the
corresponding bit in the IE register is high. In the serial ISR, we check
for both TI and RI since both could have invoked interrupt.


Example 11-9
Write a program in which the 8051 gets data from P1 and sends it to
SERIAL P2 continuously while incoming data from the serial port is sent to P0.
COMMUNI- Assume that XTAL=11.0592. Set the baud rata at 9600.
CATION Solution:
INTERRUPT ORG 0000H
LJMP MAIN
ORG 23H
Use of Serial LJMP SERIAL ;jump to serial int ISR
COM in 8051 ORG 30H
(cont’) MAIN: MOV P1,#0FFH ;make P1 an input port
MOV TMOD,#20H ;timer 1, auto reload
MOV TH1,#0FDH ;9600 baud rate
MOV SCON,#50H ;8-bit,1 stop, ren enabled
MOV IE,10010000B ;enable serial int.
BACK: MOV A,P1 ;read data from port 1
SJMP BACK ;stay in loop indefinitely
...


...
SERIAL ;-----------------SERIAL PORT ISR
ORG 100H
COMMUNI- SERIAL: JB TI,TRANS;jump if TI is high
CATION MOV A,SBUF ;otherwise due to receive
INTERRUPT MOV P0,A
CLR RI
;send incoming data to P0
;clear RI since CPU doesn’t
Use of Serial TRANS: CLR TI ;clear TI since CPU doesn’t
COM in 8051 RETI
END
;return from ISR
(cont’)


Example 11-10
Write a program using interrupts to do the following:
SERIAL (a) Receive data serially and sent it to P0,
(b) Have P1 port read and transmitted serially, and a copy given to
COMMUNI- P2,
CATION (c) Make timer 0 generate a square wave of 5kHz frequency on P0.1.
INTERRUPT Assume that XTAL-11,0592. Set the baud rate at 4800.
Solution:
ORG 0
Clearing RI and LJMP MAIN
TI before RETI ORG 000BH ;ISR for timer 0
CPL P0.1 ;toggle P0.1
ORG 23H ;
LJMP SERIAL ;jump to serial interrupt ISR
ORG 30H
MAIN: MOV P1,#0FFH ;make P1 an input port
MOV TMOD,#22H;timer 1,mode 2(auto reload)
MOV TH1,#0F6H;4800 baud rate
MOV SCON,#50H;8-bit, 1 stop, ren enabled
MOV TH0,#-92 ;for 5kHZ wave
...

...
SERIAL MOV IE,10010010B ;enable serial int.
COMMUNI- SETB TR1 ;start timer 1
CATION BACK: MOV A,P1 ;read data from port 1
INTERRUPT MOV SBUF,A ;give a copy to SBUF
Clearing RI and SJMP BACK ;stay in loop indefinitely
;-----------------SERIAL PORT ISR
TI before RETI ORG 100H
(cont’) SERIAL:JB TI,TRANS;jump if TI is high
MOV A,SBUF ;otherwise due to receive
MOV P0,A ;send serial data to P0
CLR RI ;clear RI since CPU doesn’t
TRANS: CLR TI ;clear TI since CPU doesn’t
END


The TCON register holds four of the
SERIAL
COMMUNI-
interrupt flags, in the 8051 the SCON
CATION register has the RI and TI flags
INTERRUPT
Interrupt Flag Bits
Interrupt Flag
Interrupt Flag SFR Register Bit
Bits
External 0 IE0 TCON.1
External 1 IE1 TCON.3
Timer 0 TF0 TCON.5
Timer 1 TF1 TCON.7
Serial Port T1 SCON.1
Timer 2 TF2 T2CON.7 (AT89C52)
Timer 2 EXF2 T2CON.6 (AT89C52)


When the 8051 is powered up, the
INTERRUPT
PRIORITY
priorities are assigned according to
the following
In reality, the priority scheme is nothing
but an internal polling sequence in which
the 8051 polls the interrupts in the
sequence listed and responds accordingly
Interrupt Priority Upon Reset

Highest To Lowest Priority
External Interrupt 0 (INT0)
Timer Interrupt 0 (TF0)
Serial Communication (RI + TI)


Example 11-11
INTERRUPT Discuss what happens if interrupts INT0, TF0, and INT1 are
activated at the same time. Assume priority levels were set by the
PRIORITY power-up reset and the external hardware interrupts are edge-
(cont’) triggered.

Solution:
If these three interrupts are activated at the same time, they are
latched and kept internally. Then the 8051 checks all five interrupts
according to the sequence listed in Table 11-3. If any is activated, it
services it in sequence. Therefore, when the above three interrupts
are activated, IE0 (external interrupt 0) is serviced first, then timer 0
(TF0), and finally IE1 (external interrupt 1).


We can alter the sequence of interrupt
INTERRUPT
PRIORITY
priority by assigning a higher priority
(cont’) to any one of the interrupts by
programming a register called IP
(interrupt priority)
To give a higher priority to any of the
interrupts, we make the corresponding bit
in the IP register high
When two or more interrupt bits in the IP
register are set to high
While these interrupts have a higher priority
than others, they are serviced according to the
sequence of Table 11-13


Interrupt Priority Register (Bit-addressable)
INTERRUPT
PRIORITY D7 D0
(cont’) -- -- PT2 PS PT1 PX1 PT0 PX0

-- IP.7 Reserved
-- IP.6 Reserved
PT2 IP.5 Timer 2 interrupt priority bit (8052 only)
PS IP.4 Serial port interrupt priority bit
PT1 IP.3 Timer 1 interrupt priority bit
PX1 IP.2 External interrupt 1 priority bit
PT0 IP.1 Timer 0 interrupt priority bit
PX0 IP.0 External interrupt 0 priority bit

Priority bit=1 assigns high priority
Priority bit=0 assigns low priority


Example 11-12
INTERRUPT (a) Program the IP register to assign the highest priority to
INT1(external interrupt 1), then
PRIORITY (b) discuss what happens if INT0, INT1, and TF0 are activated at the
(cont’) same time. Assume the interrupts are both edge-triggered.

Solution:
(a) MOV IP,#00000100B ;IP.2=1 assign INT1 higher priority. The
instruction SETB IP.2 also will do the same thing as the above
line since IP is bit-addressable.
(b) The instruction in Step (a) assigned a higher priority to INT1 than
the others; therefore, when INT0, INT1, and TF0 interrupts are
activated at the same time, the 8051 services INT1 first, then it
services INT0, then TF0. This is due to the fact that INT1 has a
higher priority than the other two because of the instruction in
Step (a). The instruction in Step (a) makes both the INT0 and
TF0 bits in the IP register 0. As a result, the sequence in Table
11-3 is followed which gives a higher priority to INT0 over TF0


Example 11-13
INTERRUPT Assume that after reset, the interrupt priority is set the instruction
MOV IP,#00001100B. Discuss the sequence in which the
PRIORITY interrupts are serviced.
(cont’)
Solution:
The instruction “MOV IP #00001100B” (B is for binary) and timer 1
(TF1)to a higher priority level compared with the reset of the
interrupts. However, since they are polled according to Table,
they will have the following priority.

Highest Priority External Interrupt 1 (INT1)
Lowest Priority Serial Communication (RI+TI)


In the 8051 a low-priority interrupt can
INTERRUPT
PRIORITY
be interrupted by a higher-priority
interrupt but not by another low-
Interrupt inside priority interrupt
an Interrupt Although all the interrupts are latched and
kept internally, no low-priority interrupt
can get the immediate attention of the
CPU until the 8051 has finished servicing
the high-priority interrupts


To test an ISR by way of simulation
INTERRUPT
PRIORITY
can be done with simple instructions to
set the interrupts high and thereby
Triggering cause the 8051 to jump to the
Interrupt by interrupt vector table
Software ex. If the IE bit for timer 1 is set, an
instruction such as SETB TF1 will
interrupt the 8051 in whatever it is doing
and will force it to jump to the interrupt
vector table
We do not need to wait for timer 1 go roll over
to have an interrupt


The 8051 compiler have extensive
PROGRAMMING support for the interrupts
IN C
They assign a unique number to each of
the 8051 interrupts
Interrupt Name Numbers
External Interrupt 0 (INT0) 0
Timer Interrupt 0 (TF0) 1
External Interrupt 1 (INT1) 2
Timer Interrupt 1 (TF1) 3
Serial Communication (RI + TI) 4
Timer 2 (8052 only) (TF2) 5

It can assign a register bank to an ISR
This avoids code overhead due to the pushes
and pops of the R0 – R7 registers


Example 11-14
Write a C program that continuously gets a single bit of data from P1.7
PROGRAMMING and sends it to P1.0, while simultaneously creating a square wave of
200 μs period on pin P2.5. Use Timer 0 to create the square wave.
IN C Assume that XTAL = 11.0592 MHz.
(cont’)
Solution:
We will use timer 0 mode 2 (auto-reload). One half of the period is
100 μs. 100/1.085 μs = 92, and TH0 = 256 - 92 = 164 or A4H
#include <reg51.h>
sbit SW =P1^7;
sbit IND =P1^0;
sbit WAVE =P2^5;
void timer0(void) interrupt 1 {
WAVE=~WAVE; //toggle pin
}
void main() {
SW=1; //make switch input
TMOD=0x02;
TH0=0xA4; //TH0=-92
IE=0x82; //enable interrupt for timer 0
while (1) {
IND=SW; //send switch to LED
}
}

Example 11-16
Write a C program using interrupts to do the following:
PROGRAMMING (a) Receive data serially and send it to P0
(b) Read port P1, transmit data serially, and give a copy to P2
IN C (c) Make timer 0 generate a square wave of 5 kHz frequency on P0.1
(cont’) Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800.
Solution:
#include <reg51.h>
sbit WAVE =P0^1;
void timer0() interrupt 1 {
}
void serial0() interrupt 4 {
if (TI==1) {
TI=0; //clear interrupt
}
else {
P0=SBUF; //put value on pins
RI=0; //clear interrupt
}
}
.....


.....
PROGRAMMING
IN C void main() {
(cont’) unsigned char x;
P1=0xFF; //make P1 an input
TMOD=0x22;
TH1=0xF6; //4800 baud rate
SCON=0x50;
TH0=0xA4; //5 kHz has T=200us
IE=0x92; //enable interrupts
TR1=1; //start timer 1
while (1) {
x=P1; //read value from pins
SBUF=x; //put value in buffer
P2=x; //write value to pins
}
}


Example 11-17
PROGRAMMING Write a C program using interrupts to do the following:
IN C (a) Generate a 10 KHz frequency on P2.1 using T0 8-bit auto-reload
(cont’) (b) Use timer 1 as an event counter to count up a 1-Hz pulse and
display it on P0. The pulse is connected to EX1.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.
Solution:
#include <reg51.h>
sbit WAVE =P2^1;
Unsigned char cnt;
}
cnt++; //increment counter
P0=cnt; //display value on pins
}
.....


.....
PROGRAMMING
IN C void main() {
(cont’) cnt=0; //set counter to 0
TMOD=0x42;
TH0=0x-46; //10 KHz
IE=0x86; //enable interrupts
while (1); //wait until interrupted
}


8031/51 INTERFACING TO
EXTERNAL MEMORY

Chung-Ping Young
楊中平

National Cheng Kung University

The number of bits that a
SEMI- semiconductor memory chip can store
CONDUCTOR is called chip capacity
MEMORY
It can be in units of Kbits (kilobits), Mbits
(megabits), and so on
Memory
Capacity This must be distinguished from the
storage capacity of computer systems
While the memory capacity of a memory
IC chip is always given bits, the memory
capacity of a computer system is given in
bytes
16M memory chip – 16 megabits
A computer comes with 16M memory – 16
megabytes


Memory chips are organized into a
SEMI- number of locations within the IC
CONDUCTOR
Each location can hold 1 bit, 4 bits, 8 bits,
MEMORY or even 16 bits, depending on how it is
designed internally
Memory The number of locations within a memory IC
Organization depends on the address pins
The number of bits that each location can hold
is always equal to the number of data pins
To summarize
A memory chip contain 2x location, where x
is the number of address pins
Each location contains y bits, where y is
the number of data pins on the chip
The entire chip will contain 2x × y bits


One of the most important
SEMI- characteristics of a memory chip is the
CONDUCTOR speed at which its data can be
MEMORY
accessed
To access the data, the address is
Speed
presented to the address pins, the READ
pin is activated, and after a certain amount
of time has elapsed, the data shows up at
the data pins
The shorter this elapsed time, the better,
and consequently, the more expensive the
memory chip
The speed of the memory chip is
commonly referred to as its access time


Example
A given memory chip has 12 address pins and 4 data pins. Find:
SEMI- (a) The organization, and (b) the capacity.
CONDUCTOR Solution:
MEMORY (a) This memory chip has 4096 locations (212 = 4096), and
each location can hold 4 bits of data. This gives an
organization of 4096 × 4, often represented as 4K × 4.
Speed (b) The capacity is equal to 16K bits since there is a total of
(cont’) 4K locations and each location can hold 4 bits of data.

Example
A 512K memory chip has 8 pins for data. Find:
(a) The organization, and (b) the number of address pins for
this memory chip.
Solution:
(a) A memory chip with 8 data pins means that each location
within the chip can hold 8 bits of data. To find the number
of locations within this memory chip, divide the capacity
by the number of data pins. 512K/8 = 64K; therefore, the
organization for this memory chip is 64K × 8
(b) The chip has 16 address lines since 216 = 64K

ROM is a type of memory that does not
SEMI-
CONDUCTOR
lose its contents when the power is
MEMORY turned off
ROM is also called nonvolatile memory
ROM There are different types of read-only
(Read-only
memory
Memory)
PROM
EPROM
EEPROM
Flash EPROM
Mask ROM


PROM refers to the kind of ROM that
SEMI- the user can burn information into
CONDUCTOR
PROM is a user-programmable memory
MEMORY
For every bit of the PROM, there exists a
fuse
ROM
If the information burned into PROM is
PROM wrong, that PROM must be discarded
(Programmable since its internal fuses are blown
ROM)
permanently
PROM is also referred to as OTP (one-time
programmable)
Programming ROM, also called burning
ROM, requires special equipment called a
ROM burner or ROM programmer


EPROM was invented to allow making
SEMI- changes in the contents of PROM after
CONDUCTOR it is burned
MEMORY
In EPROM, one can program the memory
chip and erase it thousands of times
ROM
A widely used EPROM is called UV-
EPROM (Erasable EPROM
Programmable
ROM)
UV stands for ultra-violet
The only problem with UV-EPROM is that
erasing its contents can take up to 20
minutes
All UV-EPROM chips have a window that is
used to shine ultraviolet (UV) radiation to
erase its contents


To program a UV-EPROM chip, the
SEMI-
CONDUCTOR
following steps must be taken:
MEMORY Its contents must be erased
To erase a chip, it is removed from its socket on
ROM the system board and placed in EPROM erasure
equipment to expose it to UV radiation for 15-20
EPROM (Erasable minutes
Programmable Program the chip
ROM) To program a UV-EPROM chip, place it in the
(cont’) ROM burner
To burn code or data into EPROM, the ROM
burner uses 12.5 volts, Vpp in the UV-EPROM
data sheet or higher, depending on the EPROM
type
Place the chip back into its system board socket


There is an EPROM programmer
SEMI- (burner), and there is also separate
CONDUCTOR EPROM erasure equipment
MEMORY
The major disadvantage of UV-EPROM,
ROM is that it cannot be programmed while
in the system board
EPROM (Erasable
Programmable
Notice the pattern of the IC numbers
ROM) Ex. 27128-25 refers to UV-EPROM that has a capacity
(cont’) of 128K bits and access time of 250 nanoseconds
27xx always refers to UV-EPROM chips
For ROM chip 27128, find the number of data and address pins.
Solution:
The 27128 has a capacity of 128K bits. It has 16K × 8
organization (all ROMs have 8 data pins), which indicates that
there are 8 pins for data, and 14 pins for address (214 = 16K)


EEPROM has several advantage over
SEMI- EPROM
CONDUCTOR
Its method of erasure is electrical and
MEMORY therefore instant, as opposed to the 20-
minute erasure time required for UV-
ROM EPROM
EEPROM One can select which byte to be erased, in
(Electrically contrast to UV-EPROM, in which the entire
Erasable contents of ROM are erased
Programmable One can program and erase its contents
ROM) while it is still in the system board
EEPROM does not require an external erasure
and programming device
The designer incorporate into the system board
the circuitry to program the EEPROM


Flash EPROM has become a popular
SEMI- user-programmable memory chip since
CONDUCTOR the early 1990s
MEMORY
The process of erasure of the entire
contents takes less than a second, or might
ROM say in a flash
Flash Memory The erasure method is electrical
EPROM It is commonly called flash memory
The major difference between EEPROM
and flash memory is
Flash memory’s contents are erased, then the
entire device is erased
– There are some flash memories are recently
made so that the erasure can be done block
by block
One can erase a desired section or byte on
EEPROM

It is believed that flash memory will
SEMI- replace part of the hard disk as a mass
CONDUCTOR storage medium
MEMORY The flash memory can be programmed
while it is in its socket on the system board
ROM Widely used as a way to upgrade PC BIOS ROM
Flash memory is semiconductor memory
Flash Memory with access time in the range of 100 ns
EPROM
compared with disk access time in the
(cont’)
range of tens of milliseconds
Flash memory’s program/erase cycles must
become infinite, like hard disks
Program/erase cycle refers to the number of
times that a chip can be erased and
programmed before it becomes unusable
The program/erase cycle is 100,000 for flash
and EEPROM, 1000 for UV-EPROM

Mask ROM refers to a kind of ROM in
SEMI- which the contents are programmed by
CONDUCTOR the IC manufacturer, not user-
MEMORY
programmable
The terminology mask is used in IC
ROM
fabrication
Mask ROM Since the process is costly, mask ROM is
used when the needed volume is high and
it is absolutely certain that the contents will
not change
The main advantage of mask ROM is its
cost, since it is significantly cheaper than
other kinds of ROM, but if an error in the
data/code is found, the entire batch must
be thrown away


RAM memory is called volatile memory
SEMI-
CONDUCTOR
since cutting off the power to the IC
MEMORY will result in the loss of data
Sometimes RAM is also referred to as
RAM (Random RAWM (read and write memory), in
Access contrast to ROM, which cannot be written
Memory) to
There are three types of RAM
Static RAM (SRAM)
NV-RAM (nonvolatile RAM)
Dynamic RAM (DRAM)


Storage cells in static RAM memory are
SEMI- made of flip-flops and therefore do not
CONDUCTOR require refreshing in order to keep their
MEMORY
data
RAM The problem with the use of flip-flops
for storage cells is that each cell require
SRAM (Static at least 6 transistors to build, and the
RAM)
cell holds only 1 bit of data
In recent years, the cells have been made
of 4 transistors, which still is too many
The use of 4-transistor cells plus the use of
CMOS technology has given birth to a high-
capacity SRAM, but its capacity is far below
DRAM


NV-RAM combines the best of RAM and
SEMI- ROM
CONDUCTOR
The read and write ability of RAM, plus the
MEMORY nonvolatility of ROM
RAM NV-RAM chip internally is made of the
following components
NV-RAM It uses extremely power-efficient SRAM
(Nonvolatile RAM) cells built out of CMOS
It uses an internal lithium battery as a
backup energy source
It uses an intelligent control circuitry
The main job of this control circuitry is to
monitor the Vcc pin constantly to detect loss of
the external power supply


To ensure the integrity of the ROM
SEMI-
CONDUCTOR
contents, every system must perform
MEMORY the checksum calculation
The process of checksum will detect any
RAM corruption of the contents of ROM
The checksum process uses what is called
Checksum Byte
ROM a checksum byte
The checksum byte is an extra byte that is
tagged to the end of series of bytes of data


To calculate the checksum byte of a
SEMI-
CONDUCTOR
series of bytes of data
MEMORY Add the bytes together and drop the carries
Take the 2’s complement of the total sum,
RAM and that is the checksum byte, which
becomes the last byte of the series
Checksum Byte
ROM To perform the checksum operation,
(cont’) add all the bytes, including the
checksum byte
The result must be zero
If it is not zero, one or more bytes of data
have been changed


Assume that we have 4 bytes of hexadecimal data: 25H, 62H, 3FH, and
52H.(a) Find the checksum byte, (b) perform the checksum operation to
SEMI- ensure data integrity, and (c) if the second byte 62H has been changed
CONDUCTOR to 22H, show how checksum detects the error.
Solution:
MEMORY (a) Find the checksum byte.
25H The checksum is calculated by first adding the
+ 62H bytes. The sum is 118H, and dropping the carry,
RAM +
+
3FH
52H
we get 18H. The checksum byte is the 2’s
complement of 18H, which is E8H
118H
Checksum Byte (b) Perform the checksum operation to ensure data integrity.
25H
ROM + 62H Adding the series of bytes including the checksum
(cont’) + 3FH byte must result in zero. This indicates that all the
+ 52H bytes are unchanged and no byte is corrupted.
+ E8H
200H (dropping the carries)
(c) If the second byte 62H has been changed to 22H, show how
checksum detects the error.
25H
+ 3FH byte shows that the result is not zero, which indicates
+ 52H that one or more bytes have been corrupted.
+ E8H
1C0H (dropping the carry, we get C0H)


Dynamic RAM uses a capacitor to store
SEMI- each bit
CONDUCTOR It cuts down the number of transistors
MEMORY needed to build the cell
It requires constant refreshing due to
RAM leakage
DRAM (Dynamic The advantages and disadvantages of
RAM) DRAM memory
The major advantages are high density
(capacity), cheaper cost per bit, and lower
power consumption per bit
The disadvantages is that
it must be refreshed periodically, due to the fact
that the capacitor cell loses its charge;
While it is being refreshed, the data cannot be
accessed

In DRAM there is a problem of packing
SEMI-
CONDUCTOR
a large number of cells into a single
MEMORY chip with the normal number of pins
assigned to addresses
RAM Using conventional method of data access,
large number of pins defeats the purpose
Packing Issue in of high density and small packaging
DRAM For example, a 64K-bit chip (64K×1) must have
16 address lines and 1 data line, requiring 16
pins to send in the address
The method used is to split the address in
half and send in each half of the address
through the same pins, thereby requiring
fewer address pins


Internally, the DRAM structure is
SEMI- divided into a square of rows and
CONDUCTOR columns
MEMORY
The first half of the address is called
RAM
the row and the second half is called
column
Packing Issue in The first half of the address is sent in
DRAM through the address pins, and by activating
(cont’) RAS (row address strobe), the internal
latches inside DRAM grab the first half of
the address
After that, the second half of the address is
sent in through the same pins, and by
activating CAS (column address strobe),
the internal latches inside DRAM latch the
second half of the address

In the discussion of ROM, we noted
SEMI-
CONDUCTOR
that all of them have 8 pins for data
MEMORY This is not the case for DRAM memory
chips, which can have any of the x1, x4, x8,
RAM x16 organizations
Discuss the number of pins set aside for address in each of the
DRAM
following memory chips. (a) 16K×4 DRAM (b) 16K×4 SRAM
Organization
Solution :
Since 214 = 16K :
(a) For DRAM we have 7 pins (A0-A6) for the address pins and 2
pins for RAS and CAS
(b) For SRAM we have 14 pins for address and no pins for RAS
and CAS since they are associated only with DRAM. In both
cases we have 4 pins for the data bus.


The CPU provides the address of the
MEMORY
ADDRESS
data desired, but it is the job of the
DECODING decoding circuitry to locate the selected
memory block
Memory chips have one or more pins called
CS (chip select), which must be activated
for the memory’s contents to be accessed
Sometimes the chip select is also referred
to as chip enable (CE)


In connecting a memory chip to the
MEMORY
ADDRESS
CPU, note the following points
DECODING The data bus of the CPU is connected
(cont’) directly to the data pins of the memory chip
Control signals RD (read) and WR (memory
write) from the CPU are connected to the
OE (output enable) and WE (write enable)
pins of the memory chip
In the case of the address buses, while the
lower bits of the address from the CPU go
directly to the memory chip address pins,
the upper ones are used to activate the CS
pin of the memory chip


Normally memories are divided into
MEMORY
ADDRESS
blocks and the output of the decoder
DECODING selects a given memory block
(cont’) Using simple logic gates
Using the 74LS138
Using programmable logics


The simplest way of decoding circuitry
MEMORY
ADDRESS
is the use of NAND or other gates
DECODING The fact that the output of a NAND gate is
active low, and that the CS pin is also
Simple Logic active low makes them a perfect match
Gate Address
Decoder
A15-A12 must be 0011 in D0

order to select the chip D7

This result in the assignment A0 A0
D7 D0

of address 3000H to 3FFFH to
this memory chip A11 A11
4K*8

A12
A13
CS
A14 RD WR
A15
MEMR
MEMW


This is one of the most widely used
MEMORY address decoders
ADDRESS
The 3 inputs A, B, and C generate 8 active-
DECODING low outputs Y0 – Y7
Each Y output is connected to CS of a memory
Using 74LS138 chip, allowing control of 8 memory blocks by a
3-8 Decoder single 74LS138
In the 74LS138, where A, B, and C select
which output is activated, there are three
additional inputs, G2A, G2B, and G1
G2A and G2B are both active low, and G1 is
active high
If any one of the inputs G1, G2A, or G2B is not
connected to an address signal, they must be
activated permanently either by Vcc or ground,
depending on the activation level


74LS138 Decoder

MEMORY
Vcc GND
Y0
A Y1

ADDRESS B
C
Y2
Y4
Y3

DECODING
Y5
Y6
Y7
G2A G2B G1

Using 74LS138 Enable

Function Table

3-8 Decoder Inputs
Enable Select
G1 G2 C B A
Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

(cont’)
X H XXX H H H H H H H H
L X XXX H H H H H H H H
H L LLL L H H H H H H H
H L LLH H L H H H H H H
H L LHL H H L H H H H H D0
H L LHH H H H L H H H H
H L HLL H H H H L H H H
H L HLH H H H H H L H H D7
H L HHL H H H H H H L H
H L HHH H H H H H H H L D7 D0
A0 A0

A11 A11
4K*8

Y0
A12 A Y1
A13 B Y2
A14 C Y4 CE
A15 G2A Y3 OE Vpp
Y5
GND G2B
Y6
Vcc G1 Y7 MEMR
Vcc


Looking at the design in Figure 14-6, find the address range for the
MEMORY Following. (a) Y4, (b) Y2, and (c) Y7.

ADDRESS Solution :
DECODING (a) The address range for Y4 is calculated as follows.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Using 74LS138 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
3-8 Decoder The above shows that the range for Y4 is 4000H to 4FFFH. In Figure
(cont’) 14-6, notice that A15 must be 0 for the decoder to be activated. Y4 will
be selected when A14 A13 A12 = 100 (4 in binary). The remaining
A11-A0 will be 0 for the lowest address and 1 for the highest address.
(b) The address range for Y2 is 2000H to 2FFFH.
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
(c) The address range for Y7 is 7000H to 7FFFH.
0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


Other widely used decoders are
MEMORY
ADDRESS
programmable logic chips such as PAL
DECODING and GAL chips
One disadvantage of these chips is that
Using one must have access to a PAL/GAL
Programmable software and burner, whereas the 74LS138
Logic needs neither of these
The advantage of these chips is that they
are much more versatile since they can be
programmed for any combination of
address ranges


The 8031 chip is a ROMless version of
INTERFACING
EXTERNAL
the 8051
ROM It is exactly like any member of the 8051
family as far as executing the instructions
and features are concerned, but it has no
on-chip ROM
To make the 8031 execute 8051 code, it
must be connected to external ROM
memory containing the program code
8031 is ideal for many systems where
the on-chip ROM of 8051 is not
sufficient, since it allows the program
size to be as large as 64K bytes


For 8751/89C51/DS5000-based system,
INTERFACING
EXTERNAL
we connected the EA pin to Vcc to
ROM indicate that the program code is
stored in the microcontroller’s on-chip
EA Pin ROM
To indicate that the program code is stored
in external ROM, this pin must be
connected to GND
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST
(RXD)P3.0
9
10
8051 32
31
P0.7(AD7)
-EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


Since the PC (program counter) of the
INTERFACING
EXTERNAL
8031/51 is 16-bit, it is capable of
ROM accessing up to 64K bytes of program
code
P0 and P2 in In the 8031/51, port 0 and port 2 provide
Providing the 16-bit address to access external
Address memory
P0 provides the lower 8 bit address A0 – A7, and
P1.0
P1.1
1
2
40
39
38
Vcc
P0.0(AD0) P2 provides the upper 8 bit address A8 – A15
P1.2 3 P0.1(AD1)

P0 is also used to provide the 8-bit data bus
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6
P1.7
RST
7
8
9
34
33
32
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
D0 – D7
8051 31
P0.0 – P0.7 are used for both the address
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)

and data paths
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)

address/data multiplexing
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


ALE (address latch enable) pin is an
INTERFACING
EXTERNAL
output pin for 8031/51
ROM ALE = 0, P0 is used for data path
ALE = 1, P0 is used for address path
P0 and P2 in
Providing
To extract the
Address address from the P0
(cont’) pins we connect P0
P1.0
P1.1
1
2
40
39
38
Vcc
P0.0(AD0)
to a 74LS373 and
use the ALE pin to
P1.2 3 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
34

latch the address
P1.6 7 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

74LS373 D Latch

Normally ALE = 0, and P0 is used as a
INTERFACING
EXTERNAL
data bus, sending data out or bringing
ROM data in
Whenever the 8031/51 wants to use P0
P0 and P2 in
as an address bus, it puts the
Providing
Address addresses A0 – A7 on the P0 pins and
(cont’) activates ALE = 1 Address/Data Multiplexing
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


PSEN (program store enable) signal is
INTERFACING
EXTERNAL
an output signal for the 8031/51
ROM microcontroller and must be connected
to the OE pin of a ROM containing the
PSEN program code
It is important to emphasize the role of
EA and PSEN when connecting the
P1.0
P1.1
1
2
40
39
Vcc
P0.0(AD0)
8031/51 to external ROM
P1.2 3 38 P0.1(AD1)

When the EA pin is connected to GND, the
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)

8031/51 fetches opcode from external ROM
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0
8051 31 -EA/VPP
by using PSEN
10
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


The connection of the PSEN pin to the
INTERFACING
EXTERNAL
OE pin of ROM
ROM In systems based on the 8751/89C51/
DS5000 where EA is connected to Vcc,
PSEN these chips do not activate the PSEN pin
(cont’) This indicates that the on-chip ROM contains
program code
Connection to External Program ROM
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031) 30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)


In an 8751 system we could use on-
INTERFACING
EXTERNAL
chip ROM for boot code and an external
ROM ROM will contain the user’s program
We still have EA = Vcc,
On-Chip and Upon reset 8051 executes the on-chip program
Off-Chip Code first, then
ROM When it reaches the end of the on-chip ROM, it
switches to external ROM for rest of program
On-chip and Off-chip Program Code Access
8031/51 8051 8052
EA = GND EA = Vcc EA = Vcc
0000 0000 0000
On-chip On-chip
0FFF
Off 1000 1FFF
Chip Off 2000 Off
Chip Chip
~ ~ ~ ~ ~ ~
FFFF FFFF FFFF


Discuss the program ROM space allocation for each of the following
INTERFACING cases.
(a) EA = 0 for the 8751 (89C51) chip.
EXTERNAL (b) EA = Vcc with both on-chip and off-chip ROM for the 8751.
ROM (c) EA = Vcc with both on-chip and off-chip ROM for the 8752.

Solution:
On-Chip and (a) When EA = 0, the EA pin is strapped to GND, and all program
Off-Chip Code fetches are directed to external memory regardless of whether or not
ROM the 8751 has some on-chip ROM for program code. This external
ROM can be as high as 64K bytes with address space of 0000 –
(cont’) FFFFH. In this case an 8751(89C51) is the same as the 8031 system.
(b) With the 8751 (89C51) system where EA=Vcc, it fetches the
program code of address 0000 – 0FFFH from on-chip ROM since it
has 4K bytes of on-chip program ROM and any fetches from
addresses 1000H – FFFFH are directed to external ROM.
(c) With the 8752 (89C52) system where EA=Vcc, it fetches the
program code of addresses 0000 – 1FFFH from on-chip ROM since
it has 8K bytes of on-chip program ROM and any fetches from
addresses 2000H – FFFFH are directed to external ROM


The 8051 has 128K bytes of address
8051 DATA
MEMORY
space
SPACE 64K bytes are set aside for program code
Program space is accessed using the program
Data Memory counter (PC) to locate and fetch instructions
Space In some example we placed data in the code
space and used the instruction
MOVC A,@A+DPTR to get data, where C stands
for code
The other 64K bytes are set aside for data
The data memory space is accessed using the
DPTR register and an instruction called MOVX,
where X stands for external
– The data memory space must be
implemented externally


We use RD to connect the 8031/51 to
8051 DATA
MEMORY
external ROM containing data
SPACE For the ROM containing the program code,
PSEN is used to fetch the code
External ROM
for Data

8051 Connection to External Data ROM

MOVX is a widely used instruction
8051 DATA allowing access to external data
MEMORY memory space
SPACE To bring externally stored data into the
CPU, we use the instruction
MOVX MOVX A,@DPTR
Instruction An external ROM uses the 8051 data space to store the look-up table
(starting at 1000H) for DAC data. Write a program to read 30 Bytes
of these data and send it to P1.
Although both MOVC
Solution: A,@A+DPTR and
MYXDATA EQU 1000H MOVX A,@DPTR look
COUNT EQU 30 very similar, one is
…
used to get data in the
MOV DPTR,#MYXDATA
MOV R2,#COUNT code space and the
AGAIN: MOVX A,@DPTR other is used to get
MOV P1,A data in the data space
INC DPTR of the microcontroller
DJNZ R2,AGAIN

Show the design of an 8031-based system with 8K bytes of program
8051 DATA ROM and 8K bytes of data ROM.

MEMORY Solution:
SPACE Figure 14-14 shows the design. Notice the role of PSEN and RD in
each ROM. For program ROM, PSEN is used to activate both OE and
CE. For data ROM, we use RD to active OE, while CE is activated by a
MOVX Simple decoder.
Instruction
(cont’)

8031 Connection to External Data ROM and External Program ROM

To connect the 8051 to an external
8051 DATA
MEMORY
SRAM, we must use both RD (P3.7) and
SPACE WR (P3.6)

External Data
RAM

8051 Connection to External Data RAM

In writing data to external data RAM,
8051 DATA we use the instruction
MEMORY MOVX @DPTR,A
SPACE
(a) Write a program to read 200 bytes of data from P1 and save the data
in external RAM starting at RAM location 5000H.
External Data (b) What is the address space allocated to data RAM in Figure 14-15?
RAM Solution:
(cont’) (a)
RAMDATA EQU 5000H
COUNT EQU 200
MOV DPTR,#RAMDATA
MOV R3,#COUNT
AGAIN: MOV A,P1
MOVX @DPTR,A
ACALL DELAY
INC DPTR
DJNZ R3,AGAIN
HERE: SJMP HERE
(b) The data address space is 8000H to BFFFH.


Assume that we have an 8031-based
8051 DATA
MEMORY
system connected to a single 64K×8
SPACE (27512) external ROM chip
The single external ROM chip is used for
Single External both program code and data storage
ROM for Code For example, the space 0000 – 7FFFH is
and Data allocated to program code, and address space
8000H – FFFFH is set aside for data
In accessing the data, we use the MOVX
instruction


To allow a single ROM chip to provide
8051 DATA
MEMORY
both program code space and data
SPACE space, we use an AND gate to signal
the OE pin of the ROM chip
Single External
ROM for Code
and Data
(cont’)

A Single ROM for BOTH Program and Data

Assume that we need an 8031 system with 16KB of program space,
16KB of data ROM starting at 0000, and 16K of NV-RAM starting at
8051 DATA 8000H. Show the design using a 74LS138 for the address decoder.
MEMORY Solution:
SPACE The solution is diagrammed in Figure 14-17. Notice that there is no
need for a decoder for program ROM, but we need a 74LS138 decoder
For data ROM and RAM. Also notice that G1 = Vcc, G2A = GND,
8031 System G2B = GND, and the C input of the 74LS138 is also grounded since we
with ROM and Use Y0 – Y3 only. 8031 Connection to External Program ROM,

RAM Data RAM, and Data ROM


In some applications we need a large
8051 DATA
MEMORY
amount of memory to store data
SPACE The 8051 can support only 64K bytes of
external data memory since DPTR is 16-bit
Interfacing to To solve this problem, we connect A0 –
Large External A15 of the 8051 directly to the external
Memory
memory’s A0 – A15 pins, and use some
of the P1 pins to access the 64K bytes
blocks inside the single 256K×8
memory chip


8051 DATA
MEMORY
SPACE

Interfacing to
Large External
Memory
(cont’)

Figure 14-18. 8051 Accessing 256K*8 External NV-RAM


In a certain application, we need 256K bytes of NV-RAM to store data
collected by an 8051 microcontroller. (a) Show the connection of an
8051 DATA 8051 to a single 256K×8 NV-RAM chip. (b) Show how various blocks
of this single chip are accessed
MEMORY
SPACE Solution:
(a) The 256K×8 NV-RAM has 18 address pins (A0 – A17) and 8 data
lines. As shown in Figure 14-18, A0 – A15 go directly to the
Interfacing to memory chip while A16 and A17 are controlled by P1.0 and P1.1,
Large External respectively. Also notice that chip select of external RAM is
connected to P1.2 of the 8051.
Memory (b) The 256K bytes of memory are divided into four blocks, and each
(cont’) block is accessed as follows :
Chip select A17 A16
P1.2 P1.1 P1.0 Block address space
0 0 0 00000H - 0FFFFH
0 0 1 10000H - 1FFFFH
0 1 0 20000H - 2FFFFH
0 1 1 30000H - 3FFFFH
1 x x External RAM disabled
….


….
8051 DATA For example, to access the 20000H – 2FFFFH address space we need
MEMORY the following :
SPACE
CLR P1.2 ;enable external RAM
MOV DPTR,#0 ;start of 64K memory block
Interfacing to CLR P1.0 ;A16 = 0
Large External SETB
MOV
P1.1
A,SBUF
;A17 = 1 for 20000H block
;get data from serial port
Memory MOVX @DPTR,A
(cont’) INC DPTR ;next location
...


LCD is finding widespread use replacing
INTERFACING
LCD TO 8051
LEDs
The declining prices of LCD
REAL-WORLD INTERFACING I
LCD Operation The ability to display numbers, characters,
LCD, ADC, AND SENSORS and graphics
Incorporation of a refreshing controller into
the LCD, thereby relieving the CPU of the
task of refreshing the LCD
Ease of programming for characters and
graphics
Chung-Ping Young
楊中平

Dept. of Computer Science and Information Engineering Department of Computer Science and Information Engineering
National Cheng Kung University HANEL National Cheng Kung University 2

Pin Descriptions for LCD LCD Command Codes

Pin Symbol I/O Descriptions Code (Hex) Command to LCD Instruction Register
INTERFACING INTERFACING 1 Clear display screen
1 VSS -- Ground
LCD TO 8051 2 VCC -- +5V power supply
LCD TO 8051 2 Return home
4 Decrement cursor (shift cursor to left)
3 VEE -- Power supply to control contrast 6 Increment cursor (shift cursor to right)
LCD Pin 4 RS I RS=0 to select command register, LCD Command 5 Shift display right
Descriptions RS=1 to select data register Codes 7 Shift display left
5 R/W I R/W=0 for write, 8 Display off, cursor off
R/W=1 for read A Display off, cursor on
6 E I/O Enable C Display on, cursor off
used by the
7 DB0 I/O The 8-bit data bus LCD to latch E Display on, cursor blinking
- Send displayed 8 DB1 I/O The 8-bit data bus information F Display on, cursor blinking
information or presented to 10 Shift cursor position to left
9 DB2 I/O The 8-bit data bus
instruction its data bus 14 Shift cursor position to right
command codes to 10 DB3 I/O The 8-bit data bus
18 Shift the entire display to the left
the LCD 11 DB4 I/O The 8-bit data bus 1C Shift the entire display to the right
- Read the contents 12 DB5 I/O The 8-bit data bus 80 Force cursor to beginning to 1st line
of the LCD’s 13 DB6 I/O The 8-bit data bus C0 Force cursor to beginning to 2nd line
internal registers 14 DB7 I/O The 8-bit data bus 38 2 lines and 5x7 matrix

Department of Computer Science and Information Engineering Department of Computer Science and Information Engineering

1

MOV A,#’N’ ;display letter N
To send any of the commands to the LCD, make pin RS=0. For data, ACALL DATAWRT ;call display subroutine
make RS=1. Then send a high-to-low pulse to the E pin to enable the ACALL DELAY ;give LCD some time
INTERFACING internal latch of the LCD. This is shown in the code below. INTERFACING MOV A,#’O’ ;display letter O
ACALL DATAWRT ;call display subroutine
LCD TO 8051 ;calls a time delay before sending next data/command
;P1.0-P1.7 are connected to LCD data pins D0-D7
LCD TO 8051 AGAIN: SJMP AGAIN ;stay here
COMNWRT: ;send command to LCD
;P2.0 is connected to RS pin of LCD
Sending Codes ;P2.1 is connected to R/W pin of LCD Sending Codes MOV
CLR
P1,A
P2.0
;copy reg A to port 1
;RS=0 for command
and Data to ;P2.2 is connected to E pin of LCD and Data to CLR P2.1 ;R/W=0 for write
ORG
LCDs w/ Time MOV A,#38H ;INIT. LCD 2 LINES, 5X7 MATRIX LCDs w/ Time SETB
CLR
P2.2
P2.2
;E=1 for high pulse
;E=0 for H-to-L pulse
Delay ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
Delay RET
MOV A,#0EH ;display on, cursor on (cont’) DATAWRT: ;write data to LCD
8051 8051 MOV P1,A ;copy reg A to port 1
VCC ACALL COMNWRT ;call command subroutine VCC
CLR P2.0 ;RS=0 for command
P1.0 D0 P1.0 D0
10k ACALL DELAY ;give LCD some time 10k CLR P2.1 ;R/W=0 for write
VEE VEE
LCD
POT MOV A,#01 ;clear LCD LCD
POT
SETB P2.2 ;E=1 for high pulse
ACALL COMNWRT ;call command subroutine CLR P2.2 ;E=0 for H-to-L pulse
P1.7 D7 VSS P1.7 D7 VSS
ACALL DELAY ;give LCD some time RET
RS R/W E MOV A,#06H ;shift cursor right RS R/W E
DELAY: MOV R3,#50 ;50 or higher for fast CPUs
ACALL COMNWRT ;call command subroutine HERE2: MOV R4,#255 ;R4 = 255
P2.0 ACALL DELAY ;give LCD some time P2.0 HERE: DJNZ R4,HERE ;stay until R4 becomes 0
MOV A,#84H ;cursor at line 1, pos. 4 DJNZ R3,HERE2
P2.1 P2.1
ACALL COMNWRT ;call command subroutine RET
P2.2 ACALL DELAY ;give LCD some time P2.2 END


;Check busy flag before sending data, command to LCD COMMAND:
;p1=data pin ACALL READY ;is LCD ready?
INTERFACING ;P2.0 connected to RS pin INTERFACING MOV
CLR
P1,A
P2.0
;issue command code
;RS=0 for command
LCD TO 8051 ;P2.1 connected to R/W pin
;P2.2 connected to E pin LCD TO 8051 CLR P2.1 ;R/W=0 to write to LCD
SETB P2.2 ;E=1 for H-to-L pulse
ORG
Sending Codes Sending Codes
CLR P2.2 ;E=0,latch in
MOV A,#38H ;init. LCD 2 lines ,5x7 matrix RET
To read the command register,
and Data to and Data to
ACALL COMMAND ;issue command DATA_DISPLAY:
MOV A,#0EH ;LCD on, cursor on ACALL READY ;is LCD we make R/W=1, RS=0, and a
ready?
LCDs w/ Busy ACALL COMMAND ;issue command LCDs w/ Busy MOV P1,A ;issue data pulse for the E pin.
H-to-L
MOV A,#01H ;clear LCD command
Flag Flag
SETB P2.0 ;RS=1 for data
ACALL COMMAND ;issue command CLR P2.1 ;R/W =0 to write to LCD
MOV A,#06H ;shift cursor right (cont’) SETB P2.2 ;E=1 for H-to-L pulse
8051 VCC ACALL COMMAND ;issue command 8051 VCC
P1.0 D0 MOV A,#86H ;cursor: line 1, pos. 6 P1.0 D0 RET
10k 10k READY:
VEE
POT
ACALL COMMAND ;command subroutine VEE
POT
LCD MOV A,#’N’ ;display letter N LCD SETB P1.7 ;make P1.7 input port
P1.7 D7 VSS ACALL DATA_DISPLAY P1.7 D7 VSS
CLR P2.0 ;RS=0 access command reg
MOV A,#’O’ ;display letter O SETB P2.1 ;R/W=1 read command reg
RS R/W E RS R/W E
ACALL DATA_DISPLAY ;read command reg and check busy flag
HERE:SJMP HERE ;STAY HERE BACK:SETB P2.2 ;E=1 for H-to-L pulse
P2.0 P2.0 CLR P2.2 ;E=0 H-to-L pulse
JB P1.7,BACK ;stay until busy flag=0
P2.1 P2.1
RET
P2.2 P2.2 END If bit 7 (busy flag) is high, the
LCD is busy and no information
should be issued to it.

2

LCD Timing
One can put data at any location in the
INTERFACING INTERFACING
LCD TO 8051
LCD and the following shows address LCD TO 8051
tDSW = Data set up time
= 195 ns (minimum)
locations and how they are accessed Data
LCD Data RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LCD Data tH = Data hold time
Sheet Sheet
tH = 10 ns (minimum)
0 0 1 A A A A A A A E tDSW

(cont’)
R/W tAS tPWH tAH

AAAAAAA=000_0000 to 010_0111 for line1
RS
AAAAAAA=100_0000 to 110_0111 for line2 tAH = Hold time after E has
The upper address
come down for both RS and
range can go as LCD Addressing for the LCDs of 40×2 size
R/W = 10 ns (minimum)
high as 0100111
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
for the 40- tPWH = Enable pulse width
character-wide Line1 (min) 1 0 0 0 0 0 0 0 = 450 ns (minimum)
LCD, which Line1 (max) 1 0 1 0 0 1 1 1
tAS = Set up time prior to E
corresponds to Line2 (min) 1 1 0 0 0 0 0 0 (going high) for both RS and
locations 0 to 39 Line2 (max) 1 1 1 0 0 1 1 1 R/W = 140 ns (minimum)


ADCs (analog-to-digital converters) are ADC804 IC is an analog-to-digital
TO ADC AND
among the most widely used devices TO ADC AND
converter
SENSORS for data acquisition SENSORS It works with +5 volts and has a resolution
A physical quantity, like temperature, of 8 bits
ADC Devices pressure, humidity, and velocity, etc., is ADC804 Chip Conversion time is another major factor in
converted to electrical (voltage, current) judging an ADC
signals using a device called a transducer, Conversion time is defined as the time it takes
or sensor the ADC to convert the analog input to a digital
(binary) number
We need an analog-to-digital converter In ADC804 conversion time varies depending on
to translate the analog signals to digital the clocking signals applied to CLK R and CLK IN
numbers, so microcontroller can read pins, but it cannot be faster than 110 µs

them


3

+5V power supply

CLK IN and CLK R
or a reference
voltage when
INTERFACING Differential analog
+5V INTERFACING
CLK IN is an input pin connected to an
Vref/2 input is open
TO ADC AND inputs where Vin 20 (not connected) TO ADC AND
SENSORS
= Vin (+) – Vin (-) 10k
POT
6 Vin(+)
VCC
D0 18
SENSORS external clock source
Vin (-) is connected 7 D1 17
To use the internal clock generator
Vin(-)
8 D2 16
to ground and Vin A GND 15
9 D3
ADC804 Chip (+) is used as the
19
Vref /2
D4 14
13
To LEDs
ADC804 Chip (also called self-clocking), CLK IN and
analog input to be CLK R D5
(cont’) converted 10k D6
D7
12
11 (cont’) CLK R pins are connected to a capacitor
150 pF
4 CLK in 3
and a resistor, and the clock frequency
CS is an active low WR
INTR 5
+5V is determined by
1
input used to activate 1 CS normally
ADC804 2 RD open 20
f =
1.1 RC
VCC
10 D GND START 6 Vin(+) D0 18
7 D1 17
Vin(-)
Typical values are R = 10K ohms and C =
8 16
A GND D2
“output enable” 9 Vref /2 D3
15
14
a high-to-low RD pulse is
“end of conversion” “start conversion”
19
CLK R
D4
D5 13
12
150 pF
D6
used to get the 8-bit
We get f = 606 kHz and the conversion time
D7 11
When the conversion is When WR makes a low-to-
converted data out of 4
is 110 µs
high transition, ADC804 CLK in 3
finished, it goes low to signal WR
ADC804 starts converting the analog INTR 5
the CPU that the converted 1 CS
2 RD
data is ready to be picked up input value of Vin to an 8- 10 D GND
bit digital number


Vref/2 D0-D7
TO ADC AND It is used for the reference voltage TO ADC AND The digital data output pins
If this pin is open (not connected), the analog These are tri-state buffered
SENSORS SENSORS
input voltage is in the range of 0 to 5 volts (the
The converted data is accessed only when CS =
same as the Vcc pin)
ADC804 Chip ADC804 Chip 0 and RD is forced low
If the analog input range needs to be 0 to 4
(cont’) volts, Vref/2 is connected to 2 volts (cont’) To calculate the output voltage, use the
following formula
Vref/2 Relation to Vin Range
V in
D out =
+5V +5V
Vref/2(v) Vin(V) Step Size ( mV)
6 Vin(+)
20
VCC
18 Not connected* 0 to 5 5/256=19.53 6 Vin(+)
20
VCC
D0 18
step size
D0
7 D1 17 7 D1 17
Vin(-)
2.0 0 to 4 4/255=15.62 Vin(-)
8
9
A GND
Vref /2
D2
D3
16
15
8
9
A GND
Vref /2
D2
D3
16
15 Dout = digital data output (in decimal),
14 1.5 0 to 3 3/256=11.71 D4 14
Vin = analog voltage, and
19 D4 19
13 13
CLK R D5
12
CLK R D5 12
D6
11 1.28 0 to 2.56 2.56/256=10 D6 11
step size (resolution) is the smallest change
D7 D7
4 CLK in
WR
3 1.0 0 to 2 2/256=7.81 4 CLK in
WR
3

INTR 5 INTR 5
1 CS 0.5 0 to 1 1/256=3.90 1 CS
2 RD 2 RD
10 10
D GND Step size is the smallest change can be discerned by an ADC D GND


4

The following steps must be followed
Analog ground and digital ground
INTERFACING INTERFACING for data conversion by the ADC804 chip
Analog ground is connected to the ground
TO ADC AND TO ADC AND Make CS = 0 and send a low-to-high pulse
of the analog Vin to pin WR to start conversion
SENSORS SENSORS
Digital ground is connected to the ground Keep monitoring the INTR pin
of the Vcc pin If INTR is low, the conversion is finished
ADC804 Chip ADC804 Chip If the INTR is high, keep polling until it goes low
(cont’) To isolate the analog Vin signal from (cont’) After the INTR has become low, we make
transient voltages caused by digital CS = 0 and send a high-to-low pulse to the
+5V switching of the output D0 – D7 RD pin to get the data out of the ADC804
6 Vin(+)
20
VCC
18
This contributes to the accuracy of the CS

digital data output
D0
7 D1 17
Vin(-)
8 16
A GND D2 15
9 D3
Vref /2
D4 14 WR
19 13
CLK R D5
12
D6
D7 11 D0-D7 Data out
End conversion
4 CLK in
WR
3 INTR
1 INTR 5 Start conversion
CS
2 RD RD
10
D GND
CS is set to low for both Read it
RD and WR pulses

The binary outputs are
ADC804 Free Running Test Mode Examine the ADC804 connection to the 8051 in Figure 12-7. Write a program to
monitored on the LED monitor the INTR pin and bring an analog input into register A. Then call a
INTERFACING +5V of the digital trainer INTERFACING hex-to ACSII conversion and data display subroutines. Do this continuously.
TO ADC AND 10k
20
VCC
TO ADC AND ;p2.6=WR (start conversion needs to L-to-H pulse)
SENSORS SENSORS
6 Vin(+) 18 ;p2.7 When low, end-of-conversion)
POT D0
7 Vin(-) D1 17
16 ;p2.5=RD (a H-to-L will read the data from ADC chip)
8 A GND D2
9 D3 15 ;p1.0 – P1.7= D0 - D7 of the ADC804
Vref /2 To LEDs
Testing 19
CLK R
D4
D5
14
13 Testing ;
MOV P1,#0FFH ;make P1 = input
ADC804 ADC804
D6 12
10k 11 BACK: CLR P2.6 ;WR = 0
150 pF D7
4 CLK in 3
(cont’) SETB P2.6 ;WR = 1 L-to-H to start conversion
WR HERE: JB P2.7,HERE ;wait for end of conversion
1 CS INTR 5 normally CLR P2.5 ;conversion finished, enable RD
2 RD open MOV A,P1 ;read the data
10 D GND START ACALL CONVERSION ;hex-to-ASCII conversion
ACALL DATA_DISPLAY;display the data
SETB p2.5 ;make RD=1 for next round
The CS input is SJMP BACK
a potentiometer used to
grounded and the
apply a 0-to-5 V analog
WR input is
voltage to input Vin (+)
connected to the
of the 804 ADC
INTR output


5

INTERFACING 8051 Connection to ADC804 with Self-Clocking INTERFACING 8051 Connection to ADC804 with Clock from XTAL2 of 8051
TO ADC AND TO ADC AND
SENSORS 8051 ADC804 5V
SENSORS 8051 ADC804 5V

P2.5 RD VCC VCC
10k 150 pF XTAL1 P2.5 RD
Testing P2.6 WR CLK R ADC804 Clock P2.6 WR
CLK in
CLK in
ADC804 from 8051
XTAL2 CLK R
P1.0 D0 10k P1.0 D0 10k
D1 Vin (+) Vin (+)
(cont’) D2
POT
XTAL2
D1
D2
POT
D3 Vin (-) Vin (-)
D Q D3
D4 Vref /2 D4 Vref /2
D5 D5
D6 CS D6 CS
P1.7 D7 Q P1.7 D7
D GND GND
P2.7 INTR A GND P2.7 INTR A GND

D Q

The frequency of crystal is too
Q
high, we use two D flip-flops
74LS74 to divide the frequency by 4


A thermistor responds to temperature The sensors of the LM34/LM35 series
INTERFACING change by changing resistance, but its INTERFACING are precision integrated-circuit
TO ADC AND TO ADC AND temperature sensors whose output
response is not linear
SENSORS SENSORS
The complexity associated with writing voltage is linearly proportional to the
software for such nonlinear devices has Fahrenheit/Celsius temperature
Interfacing LM34 and LM35
Temperature led many manufacturers to market the Temperature The LM34/LM35 requires no external
linear temperature sensor calibration since it is inherently calibrated
Sensor Sensors
It outputs 10 mV for each degree of
Temperature (C) Tf (K ohms) Fahrenheit/Celsius temperature
0 29.490
25 10.000
50 3.893
75 1.700
100 0.817
From William Kleitz, digital Electronics


6

Signal conditioning is a widely used
INTERFACING term in the world of data acquisition INTERFACING Getting Data From the Analog World
TO ADC AND TO ADC AND
It is the conversion of the signals (voltage, Analog world (temperature,
SENSORS current, charge, capacitance, and SENSORS pressure, etc. )
resistance) produced by transducers to
Signal voltage, which is sent to the input of an A- Signal
Transducer
Conditioning to-D converter Conditioning
and Signal conditioning can be a current-to- and
Interfacing voltage conversion or a signal Interfacing Signal conditioning
LM35 LM35
amplification (cont’)
The thermistor changes resistance with ADC
temperature, while the change of
resistance must be translated into voltage
in order to be of any use to an ADC Microcontroller


Example:

INTERFACING Look at the case of connecting an LM35 to an ADC804. Since the INTERFACING 8051 Connection to ADC804 and Temperature Sensor
ADC804 has 8-bit resolution with a maximum of 256 steps and the
TO ADC AND LM35 (or LM34) produces 10 mV for every degree of temperature
TO ADC AND 8051 ADC804 5V
SENSORS change, we can condition Vin of the ADC804 to produce a Vout of SENSORS VCC
2560 mV full-scale output. Therefore, in order to produce the full- XTAL1 P2.5 RD
CLK in
scale Vout of 2.56 V for the ADC804, We need to set Vref/2 = 1.28. WR
Signal Signal
P2.6 LM35 or
XTAL2 CLK R LM34
This makes Vout of the ADC804 correspond directly to the P1.0
Conditioning Conditioning
D0
temperature as monitored by the LM35. D1 Vin (+) 2.5k

and and
D2
D3 Vin (-)
D Q
Interfacing Interfacing
Temperature vs. Vout of the ADC804 D4 A GND
D5 10k

LM336
D6 Vref /2
LM35 Temp. (C) Vin (mV) Vout (D7 – D0) LM35 Q P1.7 D7
CS
Set to 1.28 V
(cont’) 0 0 0000 0000 (cont’) P2.7 INTR GND
1 10 0000 0001 Q
D
2 20 0000 0010
3 30 0000 0011 Q Notice that we use the LM336-2.5 zener diode to
fix the voltage across the 10K pot at 2.5 volts.
10 100 0000 1010
74LS74 The use of the LM336-2.5 should overcome any
30 300 0001 1110 fluctuations in the power supply

7

ADC808 has 8 analog inputs
TO ADC AND It allows us to monitor up to 8 different TO ADC AND
SENSORS transducers using only a single chip SENSORS
ADC808/809

The chip has 8-bit data output just like the
IN0 D0
ADC808/809 ADC804 ADC808/809
GND Clock Vcc

Chip The 8 analog input channels are Chip
multiplexed and selected according to table (cont’)
IN7
ADC808/809
below using three address pins, A, B, and C
D7

Vref(+) EOC
ADC808 Analog Channel Selection
Vref(-) OE
Selected Analog Channel C B A SC ALE C B A
IN0 0 0 0
(LSB)
IN1 0 0 1
IN2 0 1 0
IN3 0 1 1
IN4 1 0 0
IN5 1 0 1
IN6 1 1 0
HANEL National Cheng KungIN7
University 1 1 1 29

1. Select an analog channel by providing
INTERFACING bits to A, B, and C addresses
TO ADC AND
SENSORS 2. Activate the ALE pin
It needs an L-to-H pulse to latch in the
Steps to address
Program 3. Activate SC (start conversion ) by an
ADC808/809 H-to-L pulse to initiate conversion
4. Monitor EOC (end of conversion) to
see whether conversion is finished
5. Activate OE (output enable ) to read
data out of the ADC chip
An H-to-L pulse to the OE pin will bring
digital data out of the chip


8

LCD AND KEYBOARD
INTERFACING


Chung-Ping Young
楊中平


LCD is finding widespread use
LCD
INTERFACING
replacing LEDs
The declining prices of LCD
LCD Operation The ability to display numbers, characters,
and graphics
Incorporation of a refreshing controller
into the LCD, thereby relieving the CPU of
the task of refreshing the LCD
Ease of programming for characters and
graphics


Pin Descriptions for LCD
Pin Symbol I/O Descriptions
LCD
1 VSS -- Ground
INTERFACING 2 VCC -- +5V power supply
3 VEE -- Power supply to control contrast
LCD Pin 4 RS I RS=0 to select command register,
Descriptions RS=1 to select data register
5 R/W I R/W=0 for write,
R/W=1 for read
used by the
6 E I/O Enable LCD to latch
7 DB0 I/O The 8-bit data bus information
- Send displayed 8 DB1 I/O The 8-bit data bus presented to
information or its data bus
9 DB2 I/O The 8-bit data bus
instruction
command codes to 10 DB3 I/O The 8-bit data bus
the LCD 11 DB4 I/O The 8-bit data bus
- Read the contents 12 DB5 I/O The 8-bit data bus
of the LCD’s 13 DB6 I/O The 8-bit data bus
internal registers 14 DB7 I/O The 8-bit data bus


LCD Command Codes
Code (Hex) Command to LCD Instruction Register

LCD 1 Clear display screen
2 Return home
INTERFACING
4 Decrement cursor (shift cursor to left)
6 Increment cursor (shift cursor to right)
LCD Command 5 Shift display right
Codes 7 Shift display left
8 Display off, cursor off
A Display off, cursor on
C Display on, cursor off
E Display on, cursor blinking
F Display on, cursor blinking
10 Shift cursor position to left
14 Shift cursor position to right
18 Shift the entire display to the left
1C Shift the entire display to the right
80 Force cursor to beginning to 1st line
C0 Force cursor to beginning to 2nd line
38 2 lines and 5x7 matrix


To send any of the commands to the LCD, make pin RS=0. For data,
make RS=1. Then send a high-to-low pulse to the E pin to enable the
LCD internal latch of the LCD. This is shown in the code below.
;calls a time delay before sending next data/command
INTERFACING ;P1.0-P1.7 are connected to LCD data pins D0-D7
;P2.0 is connected to RS pin of LCD
Sending Data/ ;P2.1 is connected to R/W pin of LCD
;P2.2 is connected to E pin of LCD
Commands to ORG 0H
LCDs w/ Time MOV A,#38H ;INIT. LCD 2 LINES, 5X7 MATRIX
ACALL COMNWRT ;call command subroutine
Delay ACALL DELAY ;give LCD some time
MOV A,#0EH ;display on, cursor on
+5V
8051 VCC
P1.0 D0 ACALL DELAY ;give LCD some time
VEE 10k MOV A,#01 ;clear LCD
POT
LCD ACALL COMNWRT ;call command subroutine
P1.7 D7 VSS ACALL DELAY ;give LCD some time
RS R/W E
MOV A,#06H ;shift cursor right
P2.0
MOV A,#84H ;cursor at line 1, pos. 4
P2.1 ACALL COMNWRT ;call command subroutine
P2.2 .....

.....
MOV A,#’N’ ;display letter N
ACALL DATAWRT ;call display subroutine
LCD
MOV A,#’O’ ;display letter O
INTERFACING ACALL
AGAIN: SJMP
DATAWRT
AGAIN
;call display subroutine
;stay here
Sending Data/ MOV
CLR
P1,A
P2.0
;copy reg A to port 1
;RS=0 for command
Commands to CLR P2.1 ;R/W=0 for write
LCDs w/ Time
Delay CLR
RET
P2.2 ;E=0 for H-to-L pulse

(cont’) +5V DATAWRT: ;write data to LCD
8051 VCC MOV P1,A ;copy reg A to port 1
P1.0 D0 SETB P2.0 ;RS=1 for data
VEE 10k CLR P2.1 ;R/W=0 for write
POT
LCD SETB P2.2 ;E=1 for high pulse
P1.7 D7 VSS
CLR P2.2 ;E=0 for H-to-L pulse
RS R/W E RET
P2.0
HERE2: MOV R4,#255 ;R4 = 255
HERE: DJNZ R4,HERE ;stay until R4 becomes 0
P2.1 DJNZ R3,HERE2
RET
P2.2 END

;Check busy flag before sending data, command to LCD
;p1=data pin
LCD ;P2.0 connected to RS pin
INTERFACING ;P2.1 connected to R/W pin
;P2.2 connected to E pin
ORG 0H
Sending Data/ MOV A,#38H ;init. LCD 2 lines ,5x7 matrix
Commands to
ACALL COMMAND ;issue command
MOV A,#0EH ;LCD on, cursor on
LCDs w/ Time ACALL COMMAND ;issue command
MOV A,#01H ;clear LCD command
Delay ACALL COMMAND ;issue command
(cont’) +5V
MOV A,#06H ;shift cursor right
8051 VCC ACALL COMMAND ;issue command
P1.0 D0 MOV A,#86H ;cursor: line 1, pos. 6
10k
VEE
POT
ACALL COMMAND ;command subroutine
LCD MOV A,#’N’ ;display letter N
P1.7 D7 VSS ACALL DATA_DISPLAY
RS R/W E MOV A,#’O’ ;display letter O
ACALL DATA_DISPLAY
HERE:SJMP HERE ;STAY HERE
P2.0 .....
P2.1

P2.2


.....
COMMAND:
ACALL READY ;is LCD ready?
LCD MOV
CLR
P1,A
P2.0
;issue command code
;RS=0 for command
INTERFACING CLR P2.1 ;R/W=0 to write to LCD
Sending Codes
RET
and Data to DATA_DISPLAY:
ACALL READY ;is LCD ready?
LCDs w/ Busy MOV P1,A ;issue data
Flag
SETB P2.0 ;RS=1 for data
CLR P2.1 ;R/W =0 to write to LCD
(cont’) +5V
8051 VCC CLR P2.2 ;E=0,latch in
P1.0 D0 RET To read the command register, we make R/W=1,
VEE 10k READY:
POT RS=0, and a H-to-L pulse for the E pin.
LCD SETB P1.7 ;make P1.7 input port
P1.7 D7 VSS CLR P2.0 ;RS=0 access command reg
SETB P2.1 ;R/W=1 read command reg
RS R/W E
;read command reg and check busy flag
BACK:SETB P2.2 ;E=1 for H-to-L pulse
P2.0 CLR P2.2 ;E=0 H-to-L pulse
JB P1.7,BACK ;stay until busy flag=0
P2.1
RET If bit 7 (busy flag) is high, the LCD is busy
P2.2 END
and no information should be issued to it.

LCD Timing for Read

LCD tD = Data output delay time
INTERFACING
D0 – D7 Data
Sending Codes tD

and Data to
LCDs w/ Busy E

Flag R/W tAS tAH

(cont’)
RS
tAH = Hold time after E has

tAS = Setup time prior to E
(going high) for both RS and

Note : Read requires an L-to-H pulse for the E pin


LCD Timing for Write

LCD tDSW = Data set up time
INTERFACING = 195 ns (minimum)

Data
Sending Codes tH = Data hold time
and Data to tH = 10 ns (minimum)
LCDs w/ Busy E tDSW

Flag R/W tAS tPWH tAH

(cont’)
RS
tAH = Hold time after E has

tPWH = Enable pulse width
= 450 ns (minimum)

tAS = Setup time prior to E
(going high) for both RS and


One can put data at any location in the
LCD
INTERFACING
LCD and the following shows address
locations and how they are accessed
LCD Data Sheet RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 A A A A A A A

The upper address
range can go as LCD Addressing for the LCDs of 40×2 size
high as 0100111
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
for the 40-
character-wide Line1 (min) 1 0 0 0 0 0 0 0
LCD, which Line1 (max) 1 0 1 0 0 1 1 1
corresponds to Line2 (min) 1 1 0 0 0 0 0 0
locations 0 to 39 Line2 (max) 1 1 1 0 0 1 1 1


;Call a time delay before sending next data/command
LCD ; P1.0-P1.7=D0-D7, P2.0=RS, P2.1=R/W, P2.2=E
INTERFACING ORG 0
MOV DPTR,#MYCOM
Sending C1: CLR A
MOVC A,@A+DPTR
Information to ACALL COMNWRT ;call command subroutine
LCD Using ACALL
INC
DELAY
DPTR
;give LCD some time

MOVC JZ SEND_DAT
Instruction
SJMP C1
SEND_DAT:
MOV DPTR,#MYDATA
D1: CLR A
MOVC A,@A+DPTR
ACALL DATAWRT ;call command subroutine
INC DPTR
JZ AGAIN
SJMP D1
AGAIN: SJMP AGAIN ;stay here
.....


.....
LCD MOV
CLR
P1,A
P2.0
;copy reg A to P1
;RS=0 for command
INTERFACING CLR P2.1 ;R/W=0 for write
Sending ACALL
CLR
DELAY
P2.2
;give LCD some time
;E=0 for H-to-L pulse
Information to RET
DATAWRT: ;write data to LCD
LCD Using MOV P1,A ;copy reg A to port 1
MOVC SETB
CLR
P2.0
P2.1
;RS=1 for data
;R/W=0 for write
Instruction SETB P2.2 ;E=1 for high pulse
(cont’) CLR P2.2 ;E=0 for H-to-L pulse
RET
HERE2: MOV R4,#255 ;R4 = 255
HERE: DJNZ R4,HERE ;stay until R4 becomes 0
DJNZ R3,HERE2
RET
ORG 300H
MYCOM: DB 38H,0EH,01,06,84H,0 ; commands and null
MYDATA: DB “HELLO”,0
END


Example 12-2
LCD Write an 8051 C program to send letters ‘M’, ‘D’, and ‘E’ to the LCD
INTERFACING using the busy flag method.

Sending Solution:

Information to #include <reg51.h>
sfr ldata = 0x90; //P1=LCD data pins
LCD Using sbit rs = P2^0;
sbit rw = P2^1;
MOVC sbit en = P2^2;
Instruction sbit busy = P1^7;
void main(){
(cont’) lcdcmd(0x38);
lcdcmd(0x0E);
lcdcmd(0x01);
lcdcmd(0x06);
lcdcmd(0x86); //line 1, position 6
lcdcmd(‘M’);
lcdcmd(‘D’);
lcdcmd(‘E’);
}
.....


.....
LCD void lcdcmd(unsigned char value){
lcdready(); //check the LCD busy flag
INTERFACING ldata = value; //put the value on the pins
rs = 0;
Sending rw = 0;
en = 1; //strobe the enable pin
Information to MSDelay(1);
LCD Using en = 0;
return;
MOVC }
Instruction void lcddata(unsigned char value){
(cont’) lcdready(); //check the LCD busy flag
ldata = value; //put the value on the pins
rs = 1;
rw = 0;
MSDelay(1);
en = 0;
return;
}
.....


.....
LCD void lcdready(){
INTERFACING busy = 1;
rs = 0;
//make the busy pin at input

rw = 1;
Sending while(busy==1){ //wait here for busy flag
Information to MSDelay(1);
LCD Using en = 1;
}
MOVC
Instruction void lcddata(unsigned int itime){
unsigned int i, j;
(cont’) for(i=0;i<itime;i++)
for(j=0;j<1275;j++);
}


Keyboards are organized in a matrix of
KEYBOARD
INTERFACING
rows and columns
The CPU accesses both rows and columns
through ports
Therefore, with two 8-bit ports, an 8 x 8 matrix
of keys can be connected to a microprocessor
When a key is pressed, a row and a
column make a contact
Otherwise, there is no connection between
rows and columns
In IBM PC keyboards, a single
microcontroller takes care of hardware
and software interfacing


A 4x4 matrix connected to two ports
KEYBOARD
INTERFACING The rows are connected to an output port
and the columns are connected to an
Scanning and input port
Matrix Keyboard Connection to ports
Identifying the
Key Vcc

3 2 1 0
D0
7 6 5 4
D1 If no key has
B A 9 8 been pressed,
If all the rows are D2 reading the
grounded and a key F E D C input port will
is pressed, one of D3 yield 1s for all
the columns will columns since
have 0 since the key Port 1 they are all
pressed provides the connected to
(Out) D3 D2 D1 D0 Port 2
path to ground high (Vcc)
(In)

It is the function of the microcontroller
KEYBOARD to scan the keyboard continuously to
INTERFACING detect and identify the key pressed
To detect a pressed key, the
Grounding microcontroller grounds all rows by
Rows and providing 0 to the output latch, then it
Reading reads the columns
Columns If the data read from columns is D3 – D0 =
1111, no key has been pressed and the
process continues till key press is detected
If one of the column bits has a zero, this
means that a key press has occurred
For example, if D3 – D0 = 1101, this means that
a key in the D1 column has been pressed
After detecting a key press, microcontroller will
go through the process of identifying the key


Starting with the top row, the
KEYBOARD microcontroller grounds it by providing
INTERFACING a low to row D0 only
It reads the columns, if the data read is all
Grounding
1s, no key in that row is activated and the
Rows and process is moved to the next row
Reading
Columns It grounds the next row, reads the
(cont’) columns, and checks for any zero
This process continues until the row is
identified
After identification of the row in which
the key has been pressed
Find out which column the pressed key
belongs to


Example 12-3
KEYBOARD From Figure 12-6, identify the row and column of the pressed key for
each of the following.
INTERFACING (a) D3 – D0 = 1110 for the row, D3 – D0 = 1011 for the column
(b) D3 – D0 = 1101 for the row, D3 – D0 = 0111 for the column
Grounding Solution :
Rows and From Figure 13-5 the row and column can be used to identify the key.
Reading (a) The row belongs to D0 and the column belongs to D2; therefore,
key number 2 was pressed.
Columns (b) The row belongs to D1 and the column belongs to D3; therefore,
(cont’) key number 7 was pressed.

3 2 1 0
D0
7 6 5 4
D1
B A 9 8
D2
F E D C
D3
Vcc
Port 1
(Out) D3 D2 D1 D0 Port 2
(In)


Program 12-4 for detection and
KEYBOARD
INTERFACING
identification of key activation goes
through the following stages:
Grounding 1. To make sure that the preceding key has
Rows and been released, 0s are output to all rows
Reading at once, and the columns are read and
Columns checked repeatedly until all the columns
(cont’) are high
When all columns are found to be high, the
program waits for a short amount of time
before it goes to the next stage of waiting for
a key to be pressed


2. To see if any key is pressed, the columns
KEYBOARD are scanned over and over in an infinite
INTERFACING loop until one of them has a 0 on it
Remember that the output latches connected
Grounding to rows still have their initial zeros (provided
Rows and in stage 1), making them grounded
Reading After the key press detection, it waits 20 ms
Columns for the bounce and then scans the columns
(cont’) again
(a) it ensures that the first key press
detection was not an erroneous one due a
spike noise
(b) the key press. If after the 20-ms delay the
key is still pressed, it goes back into the
loop to detect a real key press


3. To detect which row key press belongs to,
KEYBOARD it grounds one row at a time, reading the
INTERFACING columns each time
If it finds that all columns are high, this means
that the key press cannot belong to that row
Grounding – Therefore, it grounds the next row and
Rows and continues until it finds the row the key
press belongs to
Reading Upon finding the row that the key press
Columns belongs to, it sets up the starting address for
(cont’) the look-up table holding the scan codes (or
ASCII) for that row
4. To identify the key press, it rotates the
column bits, one bit at a time, into the
carry flag and checks to see if it is low
Upon finding the zero, it pulls out the ASCII
code for that key from the look-up table
otherwise, it increments the pointer to point to
the next element of the look-up table

Flowchart for Program 12-4
1
KEYBOARD
Read all columns
INTERFACING Start

Grounding Ground all rows
no All keys
down?
Rows and
yes
Reading Read all columns
Columns Wait for debounce
(cont’)
All keys
open? Read all columns

yes
no no All keys
1 down?
yes

2


2
KEYBOARD
INTERFACING
Ground next row

Grounding
Rows and no All keys
down?
Reading
yes
Columns
(cont’) Find which key
is pressed

Get scan code
from table

Return


Program 12-4: Keyboard Program
KEYBOARD ;keyboard subroutine. This program sends the ASCII
INTERFACING ;code for pressed key to P0.1
;P1.0-P1.3 connected to rows, P2.0-P2.3 to column

Grounding MOV P2,#0FFH ;make P2 an input port
K1: MOV P1,#0 ;ground all rows at once
Rows and MOV A,P2 ;read all col
Reading ;(ensure keys open)
ANL A,00001111B ;masked unused bits
Columns CJNE A,#00001111B,K1 ;till all keys release
(cont’) K2: ACALL DELAY ;call 20 msec delay
MOV A,P2 ;see if any key is pressed
ANL A,00001111B ;mask unused bits
CJNE A,#00001111B,OVER;key pressed, find row
SJMP K2 ;check till key pressed
OVER: ACALL DELAY ;wait 20 msec debounce time
MOV A,P2 ;check key closure
ANL A,00001111B ;mask unused bits
CJNE A,#00001111B,OVER1;key pressed, find row
SJMP K2 ;if none, keep polling
....


....
KEYBOARD OVER1: MOV P1, #11111110B ;ground row 0
INTERFACING MOV A,P2 ;read all columns
ANL A,#00001111B ;mask unused bits
CJNE A,#00001111B,ROW_0 ;key row 0, find col.
Grounding MOV P1,#11111101B ;ground row 1
Rows and MOV A,P2 ;read all columns
Reading ANL A,#00001111B ;mask unused bits
Columns MOV P1,#11111011B ;ground row 2
(cont’) MOV A,P2 ;read all columns
MOV P1,#11110111B ;ground row 3
MOV A,P2 ;read all columns
LJMP K2 ;if none, false input,
;repeat
....


....
ROW_0: MOV DPTR,#KCODE0 ;set DPTR=start of row 0
KEYBOARD SJMP FIND ;find col. Key belongs to
INTERFACING ROW_1: MOV DPTR,#KCODE1 ;set DPTR=start of row
SJMP FIND ;find col. Key belongs to
Grounding SJMP FIND ;find col. Key belongs to
Rows and FIND: RRC A ;see if any CY bit low
Reading JNC MATCH ;if zero, get ASCII code

Columns
INC DPTR ;point to next col. addr
SJMP FIND ;keep searching
(cont’) MATCH: CLR A ;set A=0 (match is found)
MOVC A,@A+DPTR ;get ASCII from table
MOV P0,A ;display pressed key
LJMP K1
;ASCII LOOK-UP TABLE FOR EACH ROW
ORG 300H
KCODE0: DB ‘0’,’1’,’2’,’3’ ;ROW 0
KCODE1: DB ‘4’,’5’,’6’,’7’ ;ROW 1
KCODE2: DB ‘8’,’9’,’A’,’B’ ;ROW 2
KCODE3: DB ‘C’,’D’,’E’,’F’ ;ROW 3
END


8031/51 INTERFACING
WITH THE 8255


Chung-Ping Young
楊中平


8255 Chip
PA3 1 40 PA4
PROGRAMMING PA2 2 39 PA5
THE 8255 PA1 3 38 PA6
PA0 4 PA7
8255 is a 40- 8 37
RD 5 36 WR
8255 Features pin DIP chip CS 6
2 35 RESET
GND 7 5 34 D0
A1 8 33 D2
5
A0 9 32 D2
PC7 10
A 31 D3
PC6 11 30 D4
PC5 12 29 D5
PC4 13 28 D6
PC0 14 27 D7
PC1 15 26 VCC
PC2 16 25 PB7
PC3 17 24 PB6
PB0 18 23 PB5
PB1 19 22 PB4
PB2 20 21 PB3


8255 Block Diagram
PROGRAMMING
THE 8255 D7 – D0 PA
8
RD 2
8255 Features WR 5
PB

(cont’) A0 5
PC
A1

CS RESET

It has three separately accessible 8-
bit ports, A, B, and C
They can be programmed to
input or output and can be
changed dynamically
They have handshaking
capability


PA0 - PA7 (8-bit port A)
PROGRAMMING
Can be programmed as all input or output,
THE 8255 or all bits as bidirectional input/output
8255 Features PB0 - PB7 (8-bit port B)
(cont’) Can be programmed as all input or output,
but cannot be used as a bidirectional port
PC0 – PC7 (8-bit port C)
Can be all input or output
PA3
PA2
PA1
1
2
3
40
39
38
PA4
PA5
PA6
Can also be split into two parts:
CU (upper bits PC4 - PC7)
PA0 4 37 PA7
-RD 5 36 -WR
-CS 6 35 RESET
7 8 34
CL (lower bits PC0 – PC3)
GND D0
A1 8 33 D1
A0 9 2 32 D2
PC7 10 31 D3
each can be used for input or output
PC6 11
5 30 D4
PC5 12 5 29 D5
PC4 13 28 D6
A
Any of bits PC0 to PC7 can be
PC0 14 27 D7
PC1 15 26 Vcc
PC2 16 25 PB7
PC3 17 24 PB6
PB0
PB1
PB2
18
19
20
23
22
21
PB5
PB4
PB3
programmed individually


RD and WR
PROGRAMMING
These two active-low control signals are
THE 8255 inputs to the 8255
The RD and WR signals from the 8031/51
8255 Features
(cont’)
are connected to these inputs
D0 – D7
are connected to the data pins of the
microcontroller
PA3 1
2
40
39
PA4 allowing it to send data back and forth
between the controller and the 8255 chip
PA2 PA5
PA1 3 38 PA6
PA0 4 37 PA7
-RD 5 36 -WR

RESET
-CS 6 35 RESET
GND 7 8 34 D0
A1 8 33 D1
A0 9 2 32 D2
PC7
PC6
PC5
10
11
12
5
5
31
30
29
D3
D4
D5
An active-high signal input
Used to clear the control register
PC4 13 28 D6
PC0 14 A 27 D7
PC1 15 26 Vcc
PC2 16 25 PB7
PC3
PB0
17
18
24
23
PB6
PB5 When RESET is activated, all ports are initialized
as input ports
PB1 19 22 PB4
PB2 20 21 PB3


A0, A1, and CS (chip select)
PROGRAMMING CS is active-low
THE 8255 While CS selects the entire chip, it is A0
and A1 that select specific ports
8255 Features These 3 pins are used to access port A, B,
(cont’) C, or the control register

8255 Port Selection
CS A1 A0 Selection
0 0 0 Port A
PA3 1 40 PA4
PA2
PA1
2
3
39
38
PA5
PA6 0 0 1 Port B
PA0 4 37 PA7
-RD
-CS
5
6
36
35
-WR
RESET
0 1 0 Port C
7 8 34 D0
0 1 1 Control register
GND
A1 8 33 D1
A0 9 2 32 D2
PC7
PC6
10
11
5 31
30
D3
D4 1 X X 8255 is not selected
PC5 12 5 29 D5
PC4 13 28 D6
PC0 14 A 27 D7
PC1 15 26 Vcc
PC2 16 25 PB7
PC3 17 24 PB6
PB0 18 23 PB5
PB1 19 22 PB4
PB2 20 21 PB3


While ports A, B and C are used to
PROGRAMMING
THE 8255 input or output data, the control
register must be programmed to
Mode Selection select operation mode of three ports
of 8255
The ports of the 8255 can be
programmed in any of the following
modes:
1. Mode 0, simple I/O
Any of the ports A, B, CL, and CU can be
programmed as input out output
All bits are out or all are in
There is no signal-bit control as in P0-P3 of
8051


2. Mode 1
PROGRAMMING Port A and B can be used as input or output
THE 8255 ports with handshaking capabilities
Handshaking signals are provided by the bits
Mode Selection of port C
of 8255 3. Mode 2
(cont’)
Port A can be used as a bidirectional I/O port
with handshaking capabilities provided by port
C
Port B can be used either in mode 0 or mode
1
4. BSR (bit set/reset) mode
Only the individual bits of port C can be
programmed


8255 Control Word Format (I/O Mode)
PROGRAMMING
THE 8255 Group A Group B

Mode Selection D7 D6 D5 D4 D3 D2 D1 D0
of 8255
(cont’) 1 = I/O MODE Port A Mode Selection Port C
0 = BSR Mode 1 = Input 0 = MODE 0 (Lower
0 = Output 1 = MODE 1 PC3 – PC0)
1 = Input
0 = Output

Mode Selection Port C Port B
00 = MODE 0 (Upper 1 = Input
01 = MODE 1 Pc7 – PC4) 0 = Output
1x = Mode 2 1 = Input
0 = Output


The more commonly used term is I/O
PROGRAMMING Mode 0
THE 8255
Intel calls it the basic input/output mode
Simple I/O In this mode, any ports of A, B, or C can be
Programming
programmed as input or output
A given port cannot be both input and output at
the same time

Example 15-1
Find the control word of the 8255 for the following configurations:
(a) All the ports of A, B and C are output ports (mode 0)
(b) PA = in, PB = out, PCL = out, and PCH = out
Solution:
From Figure 15-3 we have:
(a) 1000 0000 = 80H (b)1001 0000 = 90H


The 8255 chip is programmed in any
PROGRAMMING
THE 8255 of the 4 modes
mentioned earlier by sending a byte (Intel
Connecting calls it a control word) to the control
8031/51 to register of 8255
8255 We must first find the port address
assigned to each of ports A, B ,C and
the control register
called mapping the I/O port


8255 is connected to
8051 Connection to the 8255 an 8031/51 as if it is a
PROGRAMMING RD
RAM memory
P3.7
THE 8255 P3.6
WR

A14 WR RD
P2.7
Connecting CS
PA

8031/51 to P2.0
G PB
8255 ALE
AD7
8255
PC
(cont’) P0.7 D Q A1
A1
74LS373 A0
A0

P0.0 OC D7 D0 RES
AD0

Notice the use of RD and WR signals
D7
This method of connecting an I/O
chip to a CPU is called memory
mapped I/O, since it is mapped into
D0
memory space
use memory space to access I/O
use instructions such as MOVX to
access 8255


Example 15-2

PROGRAMMING For Figure 15-4.
THE 8255 (a) Find the I/O port addresses assigned to ports A, B, C, and the
control register.
(b) Program the 8255 for ports A, B, and C to be output ports.
Connecting
(c) Write a program to send 55H and AAH to all ports continuously.
8031/51 to
8255 Solution
(cont’)
(a) The base address for the 8255 is as follows:

X 1 X x X x x x x x x x x x 0 0 = 4000H PA

X 1 X X x x x x x x x x x X 0 1 = 4001H PB

X 1 X X x x x x x x x x X X 1 0 = 4002H PC

x 1 x X x x x x x x x x x x 1 1 = 4003H CR

(b) The control byte (word) for all ports as output is 80H as seen in
Example 15-1.



PROGRAMMING (c)
THE 8255 MOV A,#80H ;control word
;(ports output)
MOV DPTR,#4003H ;load control reg
Connecting ;port address
8031/51 to MOVX @DPTR,A ;issue control word
8255 MOV A,#55H ;A = 55H
(cont’) AGAIN: MOV DPTR,#4000H ;PA address
MOVX @DPTR,A ;toggle PA bits
INC DPTR ;PB address
MOVX @DPTR,A ;toggle PB bits
INC DPTR ;PC address
MOVX @DPTR,A ;toggle PC bits
CPL A ;toggle bit in reg A
ACALL DELAY ;wait
SJMP AGAIN ;continue


8051 Connection to the 8255
PROGRAMMING P3.7
RD

THE 8255 P3.6
WR
A15
WR RD
P2.7 A14
A13 CS
Connecting A12
PA

8031/51 to P2.0
ALE
G
8255
PB

8255 P0.7
AD7
D Q A1
A1
PC

(cont’) 74LS373 A0
A0

P0.0 OC D7 D0 RES
AD0

D7

D0


Example 15-3

PROGRAMMING For Figure 15-5.
THE 8255 (a) Find the I/O port addresses assigned to ports A, B, C, and the
control register.
(b) Find the control byte for PA = in, PB = out, PC = out.
Connecting
(c) Write a program to get data from PA and send it to both B and C.
8031/51 to
8255 Solution:
(cont’)
(a) Assuming all the unused bits are 0s, the base port address for
8255 is 1000H. Therefore we have:
1000H PA
1001H PB
1002H PC
1003H Control register

(b) The control word is 10010000, or 90H.



PROGRAMMING (c)
THE 8255 MOV A,#90H ;(PA=IN, PB=OUT, PC=OUT)
MOV DPTR,#1003H ;load control register
;port address
Connecting MOVX @DPTR,A ;issue control word
8031/51 to MOV DPTR,#1000H ;PA address
8255 MOVX A,@DPTR ;get data from PA
(cont’) INC DPTR ;PB address
MOVX @DPTR, A ;send the data to PB
MOVX @DPTR, A ;send it also to PC


For the program in Example 15-3
PROGRAMMING
it is recommended that you use the EQU
THE 8255 directive for port address as shown next
APORT EQU 1000H
Connecting BPORT EQU 1001H
8031/51 to CPORT EQU 1002H
8255 CNTPORT EQU 1003H
(cont’)
MOV A,#90H ;(PA=IN, PB=OUT, PC=OUT)
MOV DPTR,#CNTPORT ;load cntr reg port addr
MOVX @DPTR,A ;issue control word
MOV DPTR,#APORT ;PA address
MOVX A,@DPTR ;get data from PA
INC DPTR ;PB address
MOVX @DPTR,A ;send the data to PB
MOVX @DPTR,A ;send it also to PC


or, see the following, also using EQU:
PROGRAMMING CONTRBYT EQU 90H ;(PA=IN, PB=OUT, PC=OUT)
THE 8255 BAS8255P EQU 1000H ;base address for 8255
MOV A,#CONTRBYT
MOV DPTR,#BAS8255P+3 ;load c port addr
Connecting MOVX @DPTR,A ;issue control word
8031/51 to MOV DPTR,#BAS8255P+3 ;PA address
. . .
8255
(cont’) Example 15-2 and 15-3
use the DPTR register since the base
address assigned to 8255 was 16-bit
if it was 8-bit, we can use
“MOVX A,@R0” and “MOVX @R0,A”
Example 15-4
use a logic gate to do address decoding
Example 15-5
use a 74LS138 for multiple 8255s

Examples 15-4 and 15-5
PROGRAMMING decode the A0 - A7 address bit
THE 8255
Examples 15-3 and 15-2
Address Aliases decode a portion of upper address A8 -
A15
this partial address decoding leads to what
is called address aliases
could have changed all x’s to various
combinations of 1s and 0s
to come up with different address
they would all refer to the same physical port
Make sure that all address aliases are
documented, so that the users know
what address are available if they want
to expanded the system

PROGRAMMING P3.7
RD

P3.6
THE 8255 WR
A7
A6 WR RD
A5
A4 CS
A3
Address Aliases A2 PA
G
(cont’) 8255 PB
ALE
AD7 PCL
P0.7 D Q A1
A1
74LS373 A0 A0 PCU

P0.0 OC D7 D0 RES
AD0

D7

D0

Figure 15-6. 8051 Connection to the 8255 for Example 15-4


Example 15-4
For Figure 15-6.
PROGRAMMING (a) Find the I/O port addresses assigned to ports A, B, C, and the
THE 8255 control register.
(b) Find the control byte for PA = out, PB = out, PC0 – PC3 = in, and
Address Aliases PC4 – PC7 =out
(cont’) (c) Write a program to get data from PB and send it to PA. In addition,
data from PCL is sent out to PCU.
Solution:

(a) The port addresses are as follows:
CS A1 A0 Address Port
0010 00 0 0 20H Port A
0010 00 0 1 21H Port B
0010 00 1 0 22H Port C
0010 00 1 1 23H Control Reg
(a) The control word is 10000011, or 83H.



PROGRAMMING (c)
THE 8255 CONTRBT EQU 83H ;PA=OUT, PB=IN, PCL=IN, PCU=OUT
APORT EQU 20H
BPORT EQU 21H
Address Aliases CPORT EQU 22H
(cont’) CNTPORT EQU 23H
...
MOV A,#CONTRBYT ;PA=OUT,PB=IN,PCL=IN,PCU=OUT
MOV R0,#CNTPORT ;LOAD CONTROL REG ADDRESS
MOVX @R0,A ;ISSUE CONTROL WORD
MOV R0,#BPORT ;LOAD PB ADDRESS
MOVX A,@R0 ;READ PB
DEC R0 ;POINT TO PA(20H)
MOVX @R0,A ;SEND IT TO PA
MOV R0,#CPORT ;LOAD PC ADDRESS
MOVX A,@R0 ;READ PCL
ANL A,#0FH ;MASK UPPER NIBBLE
SWAP A ;SWAP LOW AND HIGH NIBBLE
MOVX @R0,A ;SEND TO PCU


Example 15-5
Find the base address for the 8255 in Figure 15-7.
PROGRAMMING
THE 8255 Solution:

G1 G2B G2A C B A Address
Address Aliases A7 A6 A5 A4 A3 A2 A1 A0
(cont’) 1 0 0 0 1 0 0 0 88H

74LS138
A2 A A0
A3 B A1
A4 C
Y2
8255
A5 G2A
A6 G2B
CS
A7 G1

Figure 15-7. 8255 Decoding Using 74LS138

In 8031-based system
PROGRAMMING
THE 8255 external program ROM is an absolute must
the use of 8255 is most welcome
8031 System this is due to the fact that 3031 to
With 8255 external program ROM, we lose the two
ports P0 and P2, leaving only P1
Therefore, connecting an 8255 is the
best way to gain some extra ports.
Shown in Figure 15-8


PROGRAMMING EA P3.7 RD
P3.6 WR
THE 8255 PSEN
Vcc

A12 CE OE Vpp WR RD
P2.7 CS
A12
8031 System P2.0 A8 A8 2864 A12 PA
G (2764)
With 8255 (cont’) ALE
A7
8Kx8
8255 PB
A7 program
AD7 PC
P0.7 D Q ROM
74LS373 A0
A1
A0 A0
P0.0 OC D7 D0 RES
AD0

D7

D0

Figure 15-8. 8031 Connection to External Program ROM and the 8255


Ch 13 detailed the interface of a
8255 stepper motor to the 8051
INTERFACING
Here show stepper motor connection
Stepper Motor to the 8255 and programming in Fig
Connection To 15-9
The 8255 MOV A,#80H ;control word for PA=out
MOV R1,#CRPORT ;control reg port
address
MOVX @R1,A ;configure PA=out
MOV R1,#APORT ;load PA address
MOV A,#66H ;A=66H,stepper motor
sequence
AGAIN MOVX @R1,A ;issue motor sequence to
PA
RR A ;rotate sequence for
clockwise
ACALL DELAY ;wait
SJMP AGAIN

8255 Stepper Motor
8255 ULN2003
INTERFACING D0 D0 1 16
PA0
2 15

Stepper Motor From WR
D7 D7
WR
PA1
3 14

Connection To 8051 RD
A0
RD
A1
PA2
4 13

The 8255 (cont’) A1 A0 PA3

A2 CS RESET
Decoding
Circuitry
A7

COM
ULN2003 Connection for Stepper Motor COM
Pin 8 = GND
Pin 9 = +5V +5V

Use a separate power supply for the motor

Figure 15-9. 8255 Connection to Stepper Motor


Program 15-1
8255 Shows how to issue commands and data
INTERFACING to an LCD. See Figure 15-10
must put a long delay before issue any
LCD information to the LCD
Connection To
The 8255
Program 15-2
A repeat of Program 15-1 with the
checking of the busy flag
Notice that no DELAY is used in the main
program


LCD
8255 8255
+5V
INTERFACING PA0 D0 VPP

VEE 10K
D7 POT
LCD PA7
VSS
Connection To RS R/w E
The 8255 (cont’)
PB0
PB1
PB2

RESET

Figure 15-10. LCD Connection


;Writing commands and data to LCD without checking busy flag
;Assume PA of 8255 connected to D0-D7 of LCD and
;PB0=RS, PB1=R/W, PB2=E for LCD’s control pins connection
8255 MOV
MOV
A,#80H
R0,#CNTPORT
;all 8255 ports as output
;load control reg address
INTERFACING MOVX @R0,A ;issue control word
MOV A,#38H ;LCD:2lines, 5X7 matrix
ACALL CMDWRT ;write command to LCD
LCD ACALL DELAY
MOV A,#0EH
;wait before next issue(2 ms)
;LCD command for cursor on
Connection To ACALL CMDWRT ;write command to LCD
ACALL DELAY ;wait before next issue
The 8255 (cont’) MOV A,#01H ;clear LCD
MOV A,#06H ;shift cursor right command
. . . . ;etc. for all LCD commands
MOV A,#’N’ ;display data (letter N)
ACALL DATAWRT ;send data to LCD display
MOV A,#’O’ ;display data (letter O)
ACALL DATAWRT ;send data to LCD display
. . . . ;etc. for other data
Program 15-1.

;Command write subroutine, writes instruction commands to LCD
CMDWRT: MOV R0,#APORT ;load port A address
MOVX @R0,A ;issue info to LCD data pins
8255 MOV R0,#BPORT ;load port B address
INTERFACING MOV A,#00000100B ;RS=0,R/W=0,E=1 for H-TO-L
MOVX @R0,A ;activate LCD pins RS,R/W,E
NOP ;make E pin pulse wide enough
LCD NOP

Connection To
MOV A,#00000000B ;RS=0,R/W=0,E=0 for H-To-L
MOVX @R0,A ;latch in data pin info
The 8255 (cont’) RET
;Data write subroutine, write data to be display
DATAWRY:MOV R0,#APORT ;load port A address
MOVX @R0,A ;issue info to LCD data pins
MOV R0,#BPORT ;load port B address
MOV A,#00000101B ;RS=1,R/W=0,E=1 for H-TO-L
MOVX @R0,A ;activate LCD pins RS,R/W,E
NOP
MOVX @R0,A ;latch in LCD’s data pin info
RET

Program 15-1. (cont’)

;Writing commands to the LCD without checking busy flag
;PA of 8255 connected to D0-D7 of LCD and
;PB0=RS, PB1=R/W, PB2=E for 8255 to LCD’s control pins connection
8255 MOV A,#80H ;all 8255 ports as output
INTERFACING MOV R0,#CNTPORT ;load control reg address
MOVX @R0,A ;issue control word
MOV A,#38H ;LCD:2 LINES, 5X7 matrix
LCD ACALL NCMDWRT ;write command to LCD
Connection To MOV A,#0EH ;LCD command for cursor on

The 8255 (cont’)
ACALL NCMDWRT ;write command to LCD
MOV A,#01H ;clear LCD
MOV A,#06H ;shift cursor right command
. . . . ;etc. for all LCD commands
MOV A,#’N’ ;display data (letter N)
ACALL NDATAWRT ;send data to LCD display
MOV A,#’O’ ;display data (letter O)
CALL NDATAWRT ;send data to LCD display
. . . . ;etc. for other data

Program 15-2.

;New command write subroutine with checking busy flag
NCMDWRT:MOV R2,A ;save a value
MOV A,#90H ;PA=IN to read LCD status
8255
MOV R0,#CNTPORT ;load control reg address
MOVX @R0,A ;configure PA=IN, PB=OUT
INTERFACING MOV A,#00000110B ;RS=0,R/W=1,E=1 read command
MOVX @R0,A ;RS=0,R/W=1 for RD and RS pins
LCD MOV R0,#APORT
READY: MOVX A,@R0
;load port A address
;read command reg
Connection To PLC A
JC READY
;move D7(busy flag) into carry
;wait until LCD is ready
The 8255 (cont’) MOV A,#80H ;make PA and PB output again
MOV R0,#CNTPORT ;load control port address
MOVX @R0,A ;issue control word to 8255
MOV A,R2 ;get back value to LCD
MOV R0,#APORT ;load port A address
MOVX @R0,A ;issue info to LCD’s data pins
MOVX @R0,A ;activate RS,R/W,E pins of LCD
NOP
RET

;New data write subroutine with checking busy flag
NDATAWRT:MOV R2,#A ;save a value
MOV A,#90H ;PA=IN to read LCD status,PB=out
8255
MOVX @R0,A ;configure PA=IN, PB=OUT
INTERFACING MOV A,#00000110B ;RS=0,R/W=1,E=1 read command
MOVX @R0,A ;RS=0,R/W=1 for RD and RS pins
LCD MOV R0,#APORT
READY: MOVX A,@R0
;load port A address
;read command reg
Connection To PLC A
JC READY
;move D7(busy flag) into carry
;wait until LCD is ready
The 8255 (cont’) MOV A,#80H ;make PA and PB output again
MOVX @R0,A ;issue control word to 8255
MOV A,R2 ;get back value to LCD
MOV R0,#APORT ;load port A address
MOVX @R0,A ;issue info to LCD’s data pins
MOVX @R0,A ;activate RS,R/W,E pins of LCD
NOP
RET

the following is a program for the ADC
8255 connected to 8255 as show in fig 15-
INTERFACING 11
ADC MOV
PC=IN
A,#80H ;ctrl word for PA=OUT

Connection To MOV R1,#CRPORT ;ctrl reg port address
The 8255 MOVX @R1,A ;configure PA=OUT
PC=IN
BACK: MOV R1,#CRORT ;load port C address
MOVX A,@R1 ;read PC to see if ADC is
ready
ANL A,#00000001B ;mask all except PC0
;end of conversation, now get ADC data
MOV R1,#APORT ;load PA address
MOVX A,@R1 ;A=analog data input


8255
INTERFACING ADC804

RD VCC 10k 150 pF
WR CLK R
8255 CLK IN
ADC D0 PA0 D0

Connection To Vin(+)
10k
POT
D7 Vin(-)
The 8255 (cont’)
From WR WR
8051 RD RD A GND

A0 Verf/2
A1 PA7 D7
A2 CS
Decoding PC0 INTR GND
Circuitry
A7 RESET
CS

Figure 15-11. 8255 Connection to ADC804


A unique feature of port C
OTHER MODES
OF THE 8255 The bits can be controlled individually
BSR mode allows one to set to high or
BSR low any of the PC0 to PC7, see figure
(Bit Set/Reset) 15-12.
Mode
D7 D6 D5 D4 D3 D2 D1 D0
0 x x x Bit Select S/R

BSR Not Used 000 = Bit 0 100 = Bit 4 Set=1
Mode Generally Set = 0 001 = Bit 1 101 = Bit 5 Reset=0
010 = Bit 2 110 = Bit 6
011 = Bit 3 111 = Bit 7

Figure 15-12. BSR Control Word


Example 15-6
Program PC4 of the 8255 to generate a pulse of 50 ms with 50% duty
OTHER MODES cycle.

OF THE 8255 Solution:
To program the 8255 in BSR mode, bit D7 of the control word must be
low. For PC4 to be high, we need a control word of “0xxx1001”.
BSR Likewise, for low we would need “0xxx1000” as the control word. The
x’s are for “don’t care” and generally are set to zero.
(Bit Set/Reset) MOV a,#00001001B ;control byte for PC4=1
Mode (cont’) MOV R1,#CNTPORT ;load control reg port
MOVX @R1,A ;make PC4=1
ACALL DELAY ;time delay for high pulse
MOV A,00001000B ;control byte for PC4=0
ACALL DELAY

D0
8255
D7
WR
WR
RD PA4
RD
A2 A0 A0
Decoding A1
Circuitry A1
A7 CS

Configuration for Examples 15-6, 15-7

Example 15-7
Program the 8255 in Figure 15-13 for the following.
OTHER MODES (a) Set PC2 to high.
OF THE 8255 (b) Use PC6 to generate a square
Solution:
BSR (a)
(Bit Set/Reset) MOV R0,#CNTPORT
Mode (cont’) MOV A,#0XXX0101 ;control byte
MOVX @R0,A
(b)
AGAIN MOV A,#00001101B ;PC6=1
NOV R0,#CNTPROT ;load control port add
ACALL DELAY
ACALL DELAY
MOV A,#00001100B ;PC6=0
ACALL DELAY ;time delay for low pulse
SJMP AGAIN


One of the most powerful features of 8255 is
OTHER MODES to handle handshaking signals
OF THE 8255
Handshaking refers to the process of two
intelligent devices communicating back and
8255 in Mode 1:
forth
I/O With
Example--printer
Handshaking
Capability Mode 1: outputting data with handshaking
signals
As show in Figure 15-14
A and B can be used to send data to device with
handshaking signals
Handshaking signals are provided by port C
Figure 15-15 provides a timing diagram


PA7
Control Word – Mode 1 Output
OTHER MODES Port A Output

Handshake Signals
INTEA PA0 D7 D6 D5 D4 D3 D2 D1 D0
PC7
OF THE 8255
OBFA

Port A with
1 0 1 0 1/0 1 0 x
PC6 ACKA

PC 4,5 1=Input,0=Output
Port A Output
Port A Mode 1

Port A Mode 1

Port B Output
Port B Output

Port B Mode 1
I/O Mode
8255 in Mode 1: PC3 INTRA
I/O With
INTEB
Handshaking PC1 OBFB

Handshake Signals
PC2 ACKB
Capability (cont’)

Port B with
Status Word – Mode 1 Output
D7 D6 D5 D4 D3 D2 D1 D0
PC0 INTRB

INTEA

I/O

I/O
OBFA

OBFB

INTRB
INTEB
INTRA
WR PB7
Port B Output
PB0

PC 4,5
INTEA is controlled by PC6 in BSR mode.
INTEB is controlled by PC2 in BSR mode.

8255 Mode 1 Output Diagram


OTHER MODES WR
OF THE 8255
OBF

8255 in Mode 1: INTR
I/O With
Handshaking ACK
Output

Figure 15-15. Timing Diagram for Mode 1 Output


The following paragraphs provide the
OTHER MODES
OF THE 8255
explanation of and reasoning behind
handshaking signals only for port A,
8255 in Mode 1: but in concept they re exactly the
I/O With same as for port B
Handshaking
OBFa (output buffer full for port A)
an active-low signal going out of PC7
indicate CPU has written a byte of data in port
A
OBFa must be connected to STROBE of the
receiving equipment (such as printer) to inform
it that it can now read a byte of data from the
Port A latch


ACKa (acknowledge for port A)
OTHER MODES active-low input signal received at PC6 of 8255
OF THE 8255 Through ACK, 8255 knows that the data at port
A has been picked up by the receiving device
8255 in Mode 1: When the receiving device picks up the data at
I/O With port A, it must inform the 8255 through ACK
Handshaking 8255 in turn makes OBFa high, to indicate that
Capability (cont’) the data at the port is now old data
OBFa will not go low until the CPU writes a new
byte pf data to port A

INTRa (interrupt request for port A)
Active-high signal coming out of PC3
The ACK signal is a signal of limited duration


When it goes active it makes OBFa inactive,
OTHER MODES stays low for a small amount of time and then
OF THE 8255 goes back to high
it is a rising edge of ACK that activates INTRa
by making it high
8255 in Mode 1:
This high signal on INTRa can be used to get
I/O With the attention of the CPU
Handshaking The CPU is informed through INTRa that the
Capability (cont’) printer has received the last byte and is ready
to receive another one
INTRa interrupts the CPU in whatever it is
doing and forces it to write the next byte to
port A to be printed
It is important to note that INTRa is set to 1
only if INTEa, OBF, and ACKa are all high
It is reset to zero when the CPU writes a byte
to port A


INTEa (interrupt enable for port A)
OTHER MODES The 8255 can disable INTRa to prevent it if
OF THE 8255 from interrupting the CPU
It is internal flip-plop designed to mask INTRa
8255 in Mode 1: It can be set or reset through port C in BSR
mode since the INTEa flip-flop is controlled
I/O With through PC6
Handshaking INTEb is controlled by PC2 in BSR mode
Status word
8255 enables monitoring of the status of
signals INTR, OBF, and INTE for both ports A
and B
This is done by reading port C into accumulator
and testing the bits
This feature allows the implementation of
polling instead of a hardware interrupt


To understand handshaking with the
8255, we give an overview of printer
OTHER MODES operation, handshaking signals
OF THE 8255
The following enumerates the steps of
Printer Signal
communicating with a printer
1. A byte of data is presented to the data
bus of the printer
2. The printer is informed of the presence
of a byte of data to be printed by activating
its Strobe input signal
3. whenever the printer receives the data it
informs the sender by activating an output
signal called ACK (acknowledge)
4. signal ACK initiates the process of
providing another byte of data to printer
Table 15-2 provides a list of signals for
Centronics printers

Table 15-2. DB-25 Printer Pins
Pin Description
OTHER MODES 1 Srtobe

OF THE 8255 2 Data bit 0
3 Data bit 1
4 Data bit 2
Printer Signal 5 Data bit 3
(cont’) 6 Data bit 4
7 Data bit 5
8 Data bit 6
9 Data bit 7
10 ACK (acknowledge)
11 Busy
12 Out of paper
13 Select
14 Auto feed
15 Error
16 Initialize printer
17 Select input
18 - 25 Ground


As we can see from the steps above,
OTHER MODES merely presenting a byte of data to the
OF THE 8255 printer is not enough
The printer must be informed of the
Printer Signal presence of the data
(cont’) At the time the data is sent, the printer
might be busy or out of paper
So the printer must inform the sender whenever
it finally pick up the data from its data bus
Fig 15-16 and 15-17 show DB-25 and
Centronics sides of the printer cable
Connection of the 8031/51 with the
printer and programming are left to the
reader to explore


1 13

OTHER MODES
OF THE 8255

Printer Signal
14 25
(cont’)

Figure 15-16. DB-25 Connector

18 1

36 19

Figure 15-17. 36-Pin Centronics Connector


Table 15-3. Centronics Printer Specification
Serial Return Signal Direction Description
1 19 STROBE IN STROBE pulse to read data in. Pulse width must be
OTHER MODES more than 0.5 μs at receiving terminal. The signal
level is normally “high”; read-in of data is
OF THE 8255 performed at the “low” level of this signal.
2 20 DATA 1 IN These signals represent information of the 1st to
8th bits of parallel data, respectively. Each signal is
at “high” level when data is logical “1”, and “low”
Printer Signal when logical “0”

(cont’) 3 21 DATA 2 IN ““
4 22 DATA 3 IN ““
5 23 DATA 4 IN ““
6 24 DATA 5 IN ““
7 25 DATA 6 IN ““
8 26 DATA 7 IN ““
9 27 DATA 8 IN ““
10 28 ACKNLG OUT Approximately 0.5 μs pulse; “low” indicates data
has been received and printer is ready for data.
11 29 BUSY OUT A “high” signal indicates that the printer cannot
receive data. The signal becomes “high” in the
following case: (1)during data entry, (2) during
printing operation,(3)in “off-line” status, (4)during
printer error status.
12 30 PE OUT A “high” signal indicates that printer is out of paper
13 -- SLCT OUT Indicates that the printer is in the state selected.


Table 15-3. Centronics Printer Specification (cont’)
Serial Return Signal Directi Description
on
OTHER MODES 14 -- AUTOFEEDXT IN When the signal is at ”low” level, the paper is fed
automatically one line after printing. (The signal
OF THE 8255 level can be fixed to “low” with DIP SW pin 2-3
provided on the control circuit board.)
15 -- NC -- Not used

Printer Signal 16 -- 0V -- Logic GND level

(cont’) 17 -- CHASISGND -- Printer chassis GND. In the printer, chassis GND
and the logical GND are isolated from each other.
19–30 -- GND -- “Twisted-pair return” signal; GND level
31 -- INIT IN When this signal becomes “low” the printer con-
troller is reset to its initial state and the print buffer
is cleared. Normally at “high” level; its pulse width
must be more than 50μs at receiving terminal
32 -- ERROR OUT The level of this signal becomes “low” when
printer is in “paper end”, “off-line”, and error state
33 -- GND -- Same as with pin numbers 19 t0 30
35 -- -- Pulled up to +5V dc through 4.7 K ohms resistance.
36 -- SLCTIN IN Data entry to the printer is possible only when the
level of this signal is “low” .(Internal fixing can be
carried out with DIP SW 1-8. The condition at the
time of shipment is set “low” for this signal.)


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