Four Bit adder , 4-bit adder Vlsi, Verilog

4-Bit Adder.
Theoretical and Experimental Tutorial by Amit
Suryavanshi.

4-bit adder
• A 4-bit adder is a digital circuit that performs the
addition of two 4-bit binary numbers.
• A full adder is a combinational circuit that
performs the arithmetic sum of three input bits
Ai, addend Bi and carry in C in from the previous
adder.
• Its results contain the sum Si and the carry out, C
out to the next stage.
• To design a 4-bit adder circuit we start by
designing the 1 bit full adder then connecting
the four 1-bit full adders to get the 4-bit adder.
• It is composed of four full adders connected in
series, where each full adder is responsible for
adding the corresponding bits of the two
numbers along with a carry bit from the previous
position.

Code:
module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3;
full_adder fa0(A[0],B[0],C0,S[0],C1);
endmodule
module full_adder(A,B,Ci,S,Co);
input A,B,Ci;
output S,Co;
assign S=A^B^Ci;
assign Co=(A&B) | (Ci&(A^B));
endmodule

Test bench code:
module test_4_bit;
reg[3:0] A;
reg[3:0] B;
reg C0;
wire[3:0] S;
wire C4;
four_bit_adder dut(A,B,C0,S,C4); initial begin
A=4’b0011; B=4’b0011; C0=1’b0;
#10; A=4’b1011; B=4’b0111; C0=1’b1;
#10; A=4’b1111; B=4’b1111; C0=1’b1;
#10;
end initial
#50 $finish;
endmodule

Creating Source Codes
• In the Terminal, type gedit .v or .vhdl depending on the HDL Language you are to use (ex: 4bitadder.v).
• A Blank Document opens up into which the following source code can be typed down.
Note : File name should be with HDL Extension.
a) Verify the Functionality
➢ Three Codes shall be written for implementation of 4-bit Adder as follows,
✓ fa.v Single Bit 3-Input Full Adder [Sub-Module / Function]
→
✓ fa_4bit.v Top Module for Adding 4-bit Inputs.
→
✓ fa_test.v Test bench
→
➢ To Launch Simulation tool
✓ linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG
for the first time for any design
✓ linux:/> nclaunch& // On subsequent calls to NCVERILOG
➢ It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate it using
Multiple

➢ Select Multiple Step and then select “Create cds.lib File” as
shown in below figure
➢ Click the cds.lib file and save the file by clicking on Save
option
➢ Save cds.lib file and select the correct option for cds.lib file
format based on the HDL Language and Libraries used.
➢ Select “Don’t include any libraries (verilog design)” from
“New cds.lib file” and click on “OK” as in below figure
✓ We are simulating verilog design without using any
libraries

➢ A Click “OK” in the “nclaunch: Open Design Directory”
window as shown in below figure
➢ A ‘NCLaunch window’ appears as shown in figure below
➢ Left side you can see the HDL files. Right side of the
window has worklib and snapshots directories listed.
➢ Worklib is the directory where all the compiled codes are
stored while Snapshot will have output of elaboration which
in turn goes for simulation

To perform the function simulation, the following
three steps are involved Compilation, Elaboration
and Simulation.
Step 1: Compilation:– Process to check the
correct Verilog language syntax and usage
Inputs: Supplied are Verilog design and test
bench codes
Outputs: Compiled database created in mapped
library if successful, generates report else error
reported in log file
Steps for compilation:
1. Create work/library directory (most of the
latest simulation tools creates automatically)
2. Map the work to library created (most of the
latest simulation tools creates automatically)
3. Run the compile command with compile
options
i.e Cadence IES command for compile: ncverilog
+access+rwc -compile fa.v
➢ Left side select the file and in Tools : launch
verilog compiler with current selection will get
enable. Click it to compile the code
➢ Worklib is the directory where all the compiled
codes are stored while Snapshot will have output
of elaboration which in turn goes for simulation

➢ After compilation it will come
under worklib you can see in right
side window.
➢ Select the test bench and
compile it. It will come under
worklib. Under Worklib you can see
the module and test-bench.

The cds.lib file is an ASCII text file. It defines which
libraries are accessible and where they are located. It
contains statements that map logical library names
to their physical directory paths. For this Design, you
will define a library called “worklib”
Step 2: Elaboration:– To check the port connections in
hierarchical design
Inputs: Top level design / test bench Verilog codes
Outputs: Elaborate database updated in mapped
library if successful, generates report else error
reported in log file
Steps for elaboration – Run the elaboration command
with elaborate options
1. It builds the module hierarchy
2. Binds modules to module instances
3. Computes parameter values
4. Checks for hierarchical names conflicts
5. It also establishes net connectivity and prepares all
of this for simulation

➢ After elaboration the file will come under snapshot. Select
the test bench and elaborate it.

Step 3: Simulation: – Simulate
with the given test vectors over
a period of time to observe the
output behaviour.
Inputs: Compiled and Elaborated
top level module name
Outputs: Simulation log file,
waveforms for debugging
Simulation allow to dump design
and test bench signals into a
waveform
Steps for simulation – Run the
simulation command with
simulator options

b) Synthesize the design using
Constraints and analyse reports, critical
path and Max Operating Frequency.
Step 1: Getting Started
➢ Make sure you close out all the
Incisive tool windows first.
➢ Synthesis requires three files as
follows,
✓ Liberty Files (.lib)
✓ Verilog/VHDL Files (.v or .vhdl or .vhd)
✓ SDC (Synopsis Design Constraint) File
(.sdc)
Step 2: Creating an SDC File
➢ In your terminal type “gedit
constraints_top.sdc” to create an SDC
File if you do not have one.
➢ The SDC File must contain the
following commands;

Step 3 : Performing Synthesis
➢ The Liberty files are present in the below path, /home/install/FOUNDRY/digital/nm/dig/lib/
➢ The Available technology nodes are 180nm ,90nm and 45nm.
➢ In the terminal, initialise the tools with the following commands if a new terminal is being
used. csh source /home/install/cshrc
✓ ✓
➢ The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
➢ The Following are commands to proceed,
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl counter.v
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Effort level to medium for generic, mapping and
optimization
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation

11. report_timing >
counter_timing.rep //Generates
Timing report for worst
datapath and dumps into file
12. report_area >
counter_area.rep //Generates
Synthesis Area report and
dumps into a file
13. report_power >
counter_power.rep //Generates
Power Report [Pre-Layout]
14. write_hdl > counter_netlist.v
//Creates readable Netlist File
15. write_sdc > counter_sdc.sdc
//Creates Block Level SDC

Four Bit adder , 4-bit adder Vlsi, Verilog

Four Bit adder , 4-bit adder Vlsi, Verilog

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