Download to read offline
More Related Content
Similar to HDL for Programmable Logic HDL for Programmable Logic H64HDL and H64HDPH64HDL and H64HDP
HDL for Programmable Logic HDL for Programmable Logic H64HDL and H64HDPH64HDL and H64HDP
- 1. 1 VHDL HDL forProgrammable Logic HDL for Programmable Logic H64HDL and H64HDP H64HDL and H64HDP Module Convenor: Dr. Yiqun Zhu Email: yiqun.zhu@nottingham.ac.uk Department of Electrical and Electronic Engineering University of Nottingham
- 2. 2 VHDL Session 1 Session1 HDL Course Overview HDL Course Overview
- 3. VHDL 3 HDL Course Outline(1) Total Credits H64HDL 20 credits H64HDP 10 credits Taught Semesters Autumn Pre-requisites Introduction to Electronic Engineering (H61IIC) Electronic Design (H62ELD) Target Students Third year, fourth year UG students MSc students
- 4. VHDL 4 HDL Course Outline(2) Summary of Contents Formal lectures (Nine 2-hour sessions) Tutorial classes (Three 2-hour sessions) VHDL Laboratory (Six 2.5-hour lab sessions) Message display design VHDL project (H64HDL only) ADS6149 VHDL/FPGA controller core design Assessment H64HDL H64HDP Exam (3 hours) 25% 50% Lab 25% 50% Project 50%
- 5. VHDL 5 Session 1: HDLCourse Overview Session 2: VHDL Fundamentals Session 3: Concurrent Signal Assignment Statements Session 4: Sequential Signal Assignment Statements Session 5: Testbench Design & Combinational Circuit Design Session 6: Sequential Circuit Design Session 7: Finite State Machine VHDL Design Session 8: Hierarchical VHDL Design Session 9: Parameterised VHDL Design Lecture Coverage
- 6. VHDL 6 Activities See one-pagetimetable
- 7.
- 8. VHDL 8 Please note Wednesdaylab sessions are exactly the same as Thursday and Friday ones, so you will be allocated to either Wednesday or Thursday or Friday!!! Timetable(2)
- 9. VHDL 9 Design Platforms Software Xilinx ISE 10.1 Available in the 4th floor labs (401 & 402) Xilinx ISE WebPACK 10.1 Does not include support for some larger FPGAs Can be downloaded at http://www.xilinx.com/tools/webpack.htm Mentor Graphics ModelSim SE 6.3h Available in the 4th floor labs (401 & 402) Xilinx ChipScope Pro 10.1 Available in the 4th floor hardware lab (401) Hardware Xilinx Spartan-3E Starter kit User guide at http://www.xilinx.com/support/documentation/boards_and_kits/ ug230.pdf
- 10. VHDL 10 Xilinx Spartan-3E StarterFPGA Board
- 11. VHDL 11 1. Pong P.Chu, ‘RTL Hardware Design Using VHDL’, 2006 (Hardcopies available from the library) 2. Pellerin and Taylor, ‘VHDL Made Easy’, 1997 (Hardcopies available from the library) 3. Ben Cohen, ‘VHDL Coding Styles and Methodologies’, Second Edition, 1999 (eBook available from the library) 4. Douglas L. Perry, ‘VHDL: Programming by Example’, Fourth Edition, 2002 (eBook Available from the library) 5. Synthesis and Simulation Design Guide http://www.xilinx.com/itp/xilinx10/books/docs/sim/sim.pdf 6. VHDL Frequently Asked Questions, http://www.eda.org/comp.lang.vhdl/ 7. Xilinx ISE 10.1 Quick Start Tutorial http://www.xilinx.com/itp/xilinx10/books/docs/qst/qst.pdf References
- 12. VHDL 12 HDL Languages (1) ABEL (http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_hdl_abel.htm) Advanced Boolean Expression Language Created in 1983 by Data I/O Corporation Now owned by Xilinx VHDL (http://www.eda.org/) Initiated by US DOD VHSIC Hardware Description Language VHSIC stands for Very High Speed Integrated Circuits Verilog (http://www.eda.org/) Originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985 IEEE Std 1364-1995, 1364-2001, 1364-2005 (Revision of 1364-2001) The IEEE 1364 group is no longer active and its work has been taken over by P1800 SystemVerilog (http://www.eda.org/) A major extension of the established IEEE 1364 Verilog language Developed originally by Accellera Targeted primarily at the chip implementation and verification flow IEEE Std 1800-2005
- 13. VHDL 13 HDL Languages (2) System C (http://www.systemc.org/) First introduced in 1999 Offered by the Open SystemC Initiative (OSCI) Implemented via C++ library, runs on any C++ compiler IEEE Std 1666-2005 Handel-C (http://www.agilityds.com/) Developed by Oxford hardware compilation group Based on ISO/ANSI-C Enable someone not familiar with H/W to do H/W design Available in Agility DK design suite, which is acquired by Mentor Graphics on 22nd Jan 2009, due to the credit crunch Spec-C (http://www.ics.uci.edu/~specc/) First developed in 1997 at University of California Uses its own special compiler Designed to be true superset of ANSI-C Allows timing specification
- 14. VHDL 14 VHDL Standard Developments Initiated by US DoD in 1981 All right transferred to IEEE in 1986 IEEE 1076-1987 (VHDL-87) The First VHDL Standard No signal strengths X and Z Non-standard VHDL was developed by companies!! IEEE 1076-1993 (VHDL-93) Appended standard IEEE 1164 Contains multi-valued logic 0,1,X,Z etc IEEE 1076-2002 (VHDL-2002) More on simulation added IEEE 1076-2008 The latest VHDL standard VHDL-AMS extension, 1999 Analog and Mixed Signal VHDL RTL Synthesis, 2004
- 15. VHDL 15 IEEE VHDL Standards P1076 (VHDL Language Reference Manual) P1076.1 (VHDL-AMS) VHDL Analog and Mixed-Signal extensions P1076.2 (VHDL Math Packages) Math_Real & Math_Complex P1076.3 (VHDL Synthesis Package) Numeric_bit & Numeric_std Fphdl_base_pkg (Floating-point) P1076.4 Timing VHDL Initiative Towards to ASIC Libraries (VITAL) P1076.6 (VHDL Register Transfer Level (RTL) Synthesis) VHDL Synthesis Interoperability http://www.vhdl.org/siwg/ P1164 (VHDL Multivalue Logic) Std_Logic_1164
- 16. VHDL 16 VHDL Applications Documentation Design specifications FPGA Field Programmable Gate Array Quick Time-to-Market Low cost for low volume ASIC Application Specific Integrated Circuits High Design & fabrication cost Slow Time-to-Market Low cost for huge volume
- 17. VHDL 17 System Design Specification Simulation RTL Design LogicDesign Simulation Simulation Modelling the Structure Modelling the Behaviour Automatic Gate Generation RTL VHDL Behavioural VHDL Netlist VHDL Transistor Design Simulation Layout Fabrication Simulation R, C Extract from Interconnect Transistor Modelling SPICE & Backannotate SPICE Simulation ASIC Design Flow
- 18.
- 19. VHDL 19 Design Entry Design Synthesis Design Implementation FPGAProgramming Behavioural Simulation Timing Analysis Timing Simulation In-Circuit Verification Design Verification VHDL Back Annotation FPGA Design Flow
- 20. VHDL 20 Virtex SeriesFPGAs (High performance) Virtex, introduced in 1998 and fabricated in 2.5V, 0.22 micro Virtex-E, 1999. Virtex-II, 2001. Virtex-II Pro, 2002 Virtex-4, 2004, 1.2V, 90nm, the first multi-platform FPGA Virtex-5, 2006, 1.0V, the first 65nm multi-platform FPGA Virtex-6, 2009, 0.9-1.0V, 40nm, targeted design platforms Spartan Series FPGAs (Low cost) Spartan-3E, 1.2V Gate-centric designs XC3s500e-5fg320 will be used for our lab design Spartan-6, 1.0V, released in 2009 The Low-Power, Low-Cost Silicon Foundation for Targeted Design Platforms More on www.xilinx.com Xilinx FPGA Devices
- 21. VHDL 21 Stratix SeriesFPGAs (High-Density) Cyclone Series FPGAs (Low cost) More on www.altera.com Altera FPGA Devices
- 22. VHDL 22 Antifuse Technology Military/Aerospace (Radiation-tolerant) Automotive (High-temperature) More on www.actel.com Actel FPGA Devices
- 23. VHDL 23 Why VHDL? Formalspecification language Reduces paperwork Technology and Process independence Design re-use Alternative to schematics Wide range of levels gate, RTL, behaviour, integer and real Description and simulation of complex systems Microprocessors
- 24. VHDL 24 Difficult to LearnVHDL? Before answering this, have a look at the following figure What are the synthesisable VHDL codes? Can be automatically converted into logic gates Easy to learn Synthesisable VHDL Difficult to master Simulation VHDL Lucky you Mainly focus on synthesisable VHDL Simulation only VHDL Synthesisable VHDL
- 25. VHDL 25 Compilers & Simulators All VHDL files need to be compiled before they can be simulated. Simulators for this course Mentor Graphics ModelSim SE 6.3h (Compulsory) Generic VHDL simulators ModelSim is so universal that FPGA vendors, such as Xilinx and Altera, have integrated the ModelSim into their latest FPGA tools ModelSim is a must when looking for VHDL design jobs Xilinx ISE simulator (requires Xilinx ISE) (Optional) Mixed VHDL and Verilog simulation An integrated wave editor for test bench creation Behavioral/RTL simulation prior to synthesis Timing simulation after place and route or fitting
- 26. VHDL 26 Using WebCT AccessWebCT (http://webct.nottingham.ac.uk) Temporary Access Username: eeeguest Password: eeeguest01
- 27. VHDL 27 H64HDL/H64HDP Info. inWebCT Lecture Notes Although you will be given a hardcopy of the lecture note at the beginning of the lecture session, you are able to access the electronic copy in WebCT after the corresponding lecture session. VHDL example codes Will be available after the corresponding lecture session. Solutions to VHDL exercises Will be available after next lecture session. Past exam papers Announcements
- 28. VHDL 28 Xilinx ISE 10.1Getting Started Here we use a half adder VHDL design as an example to go through the VHDL/FPGA design flow (using both ISE simulator and ModelSim) Syntax Check Functional Simulation Synthesis Implementation Timing Simulation library ieee; use ieee.std_logic_1164.all; -- entity declaration entity HalfAdder is port( a, b: in std_logic; sum, carry: out std_logic ); end HalfAdder; -- architecture body architecture HalfAdder_arch of HalfAdder is begin sum <= a xor b; carry <= a and b; end HalfAdder_arch;
- 29. VHDL 29 Xilinx ISE 10.1Getting Started Try Xilinx ISE 10.1 by yourself with the provided full adder VHDL code: library ieee; use ieee.std_logic_1164.all; -- entity declaration entity FullAdder is port( cin, a, b: in std_logic; sum, cout: out std_logic ); end FullAdder; -- architecture body architecture FullAdder_arch of FullAdder is signal x, y, z: std_logic; begin sum <= a xor b xor cin; x <= a and b; y <= a and cin; z <= b and cin; cout <= x or y or z; end FullAdder_arch;