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An Open Hardware CPU written in VHDL, synthesized with Open Source tools
- 1. Microwatt and GHDL- An Open Hardware CPU written in VHDL, synthesized with Open Source tools — Anton Blanchard IBM
- 6. Open Source Firmware Entirefirmware stack is Open Source and available on github 6
- 7. Raptor POWER9 Workstation Providesa native development environment Uses the same Open Source firmware stack 7
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- 9. POWER OpenISA Announcedin August The POWER Instruction Set Architecture is now open Royalty free, inclusive of patents OpenPOWER Foundation moves under the Linux Foundation Also released a reference implementation called Microwatt 9
- 10. Microwatt Tiny POWER core OpenISA scalar subset Written in VHDL 2008 ghdl Open Source simulation ghdl/yosys/nextpnr Open Source synthesis https://github.com/antonblanchard/microwatt 10
- 11. Microwatt Single issue In order Aimsto be simple and easy to understand Reuse from the Open Hardware world ● UART, DRAM, Ethernet 11
- 13. Language support We’ve beenable to leverage the strength of the PowerPC ecosystem Lots of stuff “just works” I use a distro toolchain for my development work We have been adding platform support for key languages Thanks to Michael Neuling, Jordan Niethe, Tom Vijlbrief and Paul Mackerras. 13
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- 20. Recent Developments LiteX (DRAM,Ethernet) - Ben Herrenschmidt and Florent Kermarrec Icache/dcache – Ben Herrenschmidt Branch predictor – Paul Mackerras Interrupts – Michael Neuling and Ben Herrenschmidt TLB – Paul Mackerras Linux – Paul Mackerras Continuous Integration – Michael Neuling Many community contributions (215 github commits) 20
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- 22. Hardware Reuse Microwatt implementsthe Wishbone bus ● Simple, open protocol, widely used in the Open Hardware world ● Allowed us to interface with LiteX project ● DRAM, Ethernet ● More to come 23
- 23. Open Source Simulationand Synthesis Simulation done using GHDL ● Great environment for testing, including CI ● Good language support, including VHDL 2008 ● Maintainer is very responsive! GHDL recently added synthesis support ● Allows completely Open Source flow for FPGA synthesis ● Also allows VHDL → Verilog conversion via yosys, and mixed language simulation and synthesis. 24
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