AI-Driven Lithography Defect Prediction with Hyperdimensional Mapping

🏅Chinese team cut lithography defects by 99 % in DUV, but... 🇨🇳 A Chinese research team has developed a new method using cryogenic electron-tomography (cryo-ET) at ~105 °C to visualise photoresist polymer clustering in DUV lithography lines, and subsequently adjust the process to reduce defect density by up to ~99 %. The method demonstrates how advanced metrology (cryo-ET) can identify ultra-fine defect origination (polymer clusters, resist microvoids) in DUV exposure lines → enabling a ~99 % yield improvement. However, when applied to EUV-patterned wafers the same method degrades overlay or pattern fidelity, making it unsuitable for EUV flows. It highlights a trade-off: the improved resist/clustering process negatively impacts EUV pattern fidelity (likely due to different resist chemistry, photon energy, and scatter behaviour), indicating DUV optimisation cannot simply be ported to EUV flows. Further, it suggests that fabs still relying on DUV multipatterning (especially in China) can gain large yield improvements cost-effectively — but moving to EUV (or High-NA EUV) still demands distinct process tuning. The work underlines metallurgical/materially-specific defect control (resist clustering) as a viable short-term competitive lever in lithography optimisation, especially in geographies where EUV tool access is limited. Moreover, it raises strategic implications: while cutting DUV defects by 99% may bolster older node flows or DUV-heavy fabs, the inability to apply the same fix to EUV means a performance gap remains for advanced nodes — reinforcing the technology divide. #Lithography #DUV #EUV #SemiconductorManufacturing #YieldOptimization #Photoresist #ProcessEngineering More information: https://lnkd.in/gYSHximX

Hello folks, We had an extremely educational session yesterday on "IC Design from concept to Silicon" by Hareesh Janakiraman sir. Deep insights into the technical and business aspects of chip design were given during the session. These included the steps from concept to production, the cost and effort involved, and how and why new chips are developed. Additionally, we looked at timing closure, DRC (Design Rule Check), pre-silicon validation, and the distinctions between hard and soft macros. We also learnt about ASML, the Dutch company that invented EUV (Extreme Ultraviolet) lithography machines, which are essential to the production of semiconductors today, and the session provided insight into contemporary chip fabrication challenges. Thank you to Hareesh Janakiraman sir for having such insightful and engaging sessions.

We've discussed how essential semiconductors are in our increasingly technological world, so here's an update on ASML’s new High-NA EUV lithography machines. Full Newsletter: https://bit.ly/3WHTHUB #semiconductors #tsmc #lithography #tech #technology

🚀 Direct Print EUV Pattern Transfer – The Etch Perspective As EUV lithography pushes below 35 nm pitch, the role of plasma etch in transferring ultra-fine patterns becomes more complex and critical. A recent study by my previous engineering manager Hiten Kothari and Steven Jaloviar highlights how tight-pitch metal layers demand careful co-optimization of lithography, film stack, and etch processes to achieve defect-free patterning for high-volume manufacturing (HVM). 🔍 Key Takeaways: Stack Co-Optimization is Essential: Resist, underlayer, and carbon hardmask selection must be tuned together to ensure robust pattern transfer and minimal defectivity. Underlayer Matters: Thin-film underlayers deposited via ALD/CVD offer superior control over fallen-line defects versus traditional spin-on films. Descum Chemistry is a Game Changer: Optimized plasma descum steps (especially fluorinated chemistries) drastically reduce microbridge and residue defects without resist loss. Directional Etch (TTT Push): Novel directional etch techniques enable selective cleaning of microbridges within trenches, preserving CD and improving yield. Future Outlook: High-NA EUV will intensify challenges in resist thickness, stochastic defects, and etch selectivity, making advanced etch chemistries and endpoint control key to continued scaling. 🔬 Bottom Line: Direct print EUV can achieve HVM readiness only through tight integration of lithography, materials, and plasma etch development, a true multidisciplinary effort advancing Moore’s Law. Please feel free to go through this amazing article from Dr. Kushner's group: https://lnkd.in/gBiuBcV4 #EUVLithography #PlasmaEtch #SemiconductorManufacturing #DefectReduction #ProcessIntegration #AdvancedNodes #MooresLaw

Inside the World of Semiconductor Metrology: Precision or Nothing If chip manufacturing is a game of precision, metrology is the referee, the scoreboard, and the replay system. Without it, you’re playing blind. Working as a Metrology Tool Development Engineer in semiconductor manufacturing is not glamorous. It’s not “just measuring wafers.” It’s being responsible for making sure the entire chip production line actually knows what it’s doing. Every nanometer matters, literally and if our measurements are off, the entire fab loses yield, time, and millions of dollars. When a wafer goes through lithography, etch, deposition, CMP such the process only thinks it knows what it did. Metrology is the reality check and definition of semiconductor! #SemiconductorIndustry #Metrology #PrecisionEngineering #processconteol #YieldEngineering #Nanotechnology #AdvancedManufacturing #SemiconductorEngineering #ChipDesign #AMAT #IndiaSemiconductorMission

Excited to share that our review, “Directed self-assembly of block copolymers for high-precision patterning in the era of extreme ultraviolet lithography,” has been published. Link: https://lnkd.in/gussry7f In this article, we highlight recent progress and the underlying chemistry and physics of the EUV + DSA strategy, advancing toward highly precise and energy-efficient patterning technologies. This review provides a comprehensive overview of the design principles of BCP materials and processing parameters, advanced metrology techniques, and pattern transfer strategies for effectively integrating DSA into next-generation nanofabrication workflows. Special thanks to my co-authors, Dr. Ki Hyun Kim Dr, Emma Vargo, Dr. Ricardo Ruiz , Dr. Gordon Craig, and Prof. Paul Nealey, and DOE-funded CHiPPS-EFRC team!

Exciting Q4 developments in semiconductor innovation: Applied Materials’ Kinex™ integrated die-to-wafer hybrid bonding system and ASML’s TWINSCAN XT:260 i-line lithography scanner are set to redefine advanced packaging for the AI era. Kinex, co-developed with Besi, enables high-volume manufacturing (HVM) of heterogeneous integration with sub-micron alignment precision, slashing interconnect resistance and boosting 3D stacking densities for next-gen AI accelerators. Meanwhile, XT:260 quadruples throughput to 270 wafers/hour, optimizing back-end lithography for fine-pitch redistribution layers (RDL) and through-silicon vias (TSVs) in multi-die systems. These breakthroughs underscore advanced packaging’s pivotal role in overcoming Moore’s Law limits, delivering energy-efficient, high-bandwidth compute via chiplet architectures and wafer-level fan-out. At IME A*STAR, we’re at the forefront of this transformation: Our full-stack ecosystem spans electrical-thermal-mechanical modeling, novel interposer designs, and prototype-to-production workflows, backed by state-of-the-art cleanrooms and partnerships with industry leaders. We’ve pioneered heterogeneous integration for AI SoCs, including CPOs for data center application. Ready to co-develop your advanced packaging roadmap? Let’s connect.

⚙️ The future of nano surface replication is rolling… For decades, mask lithography, injection moulding, and conventional flat NIL methods have been the cornerstones of nanostructure fabrication. But as industries evolve, so do their needs for scalable high-volume manufacturing. That’s where Rolling Nanoimprint Lithography (RNIL) comes in. At Stensborg, we’ve reimagined nanoreplication with our patented optical engine, delivering UV-curing directly at the nip point for precision, speed, and process flexibility. RNIL combines nanoscale fidelity with continuous, energy-efficient throughput, in Roll-to-Roll (R2R) and Roll-to-Plate (R2P) productions. What makes RNIL truly transformative is its versatility — seamlessly integrating into diverse workflows and empowering researchers, engineers, and manufacturers to experiment, iterate, and scale without material or process limitations. Learn how Rolling Nanoimprint Lithography is shortening innovation cycles and accelerating next-gen applications: https://lnkd.in/d5xNJ_HC #RollingNanoimprintLithography #RollToRoll #RollToPate #MaskLithographyAlternative #NanoReplication #UVNIL #MassProduction #Microstructures #Nanofeatures

Ever wonder if metalenses manufactured by direct nanoimprint lithography are suitable for high-energy applications? They are! We demonstrate the stability of high-efficiency all-inorganic metalenses using femtosecond laser-induced damage threshold (LIDT) testing at visible wavelengths and LIDT testing in the nanosecond regime at visible and near IR wavelengths in a recent publication in Advanced Optical Materials. https://lnkd.in/euj_uZB9 The work is a collaboration among the Watkins and Amir Arbabi groups at UMass, the Institute of Production Engineering and Photonic Technologies, TU Wien and Cerabyte GmbH. Full-scale wafer manufacturing of high-efficiency all-inorganic metalenses is available through Myrias Optics.  

I recently came across this post from ASML explaining why numerical aperture is such an important factor in wafer fabrication technology. As a student learning about semiconductor processes, I found it fascinating how even subtle optical parameters can significantly influence resolution and pattern accuracy during lithography. Posts like this remind me how complex and precise chip manufacturing really is — and how innovation in every small aspect contributes to advancing technology as a whole. Definitely worth a read for anyone interested in semiconductor engineering or nanotechnology!