lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
A minimal GPU design in Verilog to learn how GPUs work from the ground up
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
HW Design Collateral for Caliptra RoT IP
Common SystemVerilog components
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
VeeR EL2 Core
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
[UNRELEASED] FP div/sqrt unit for transprecision
RISC-V Debug Support for our PULP RISC-V Cores
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit